Techniques for reading from and/or writing to a semiconductor memory device

ABSTRACT

Techniques for reading from and/or writing to a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first memory cell array having a first plurality of memory cells arranged in a matrix of rows and columns and a second memory cell array having a second plurality of memory cells arranged in a matrix of row and columns. The apparatus may also include a data sense amplifier latch circuitry having a first input node and a second input node. The apparatus may further include a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry and a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to semiconductor memory devices and, more particularly, to techniques for reading from and/or writing to a semiconductor memory device.

BACKGROUND OF THE DISCLOSURE

A semiconductor memory device may include an electrically floating body in which an electrical charge is stored. The electrical charge stored in the electrically floating body may represent a logic high or “1” data state or a logic low or “0” data state.

Various techniques may be employed to read data from and/or write data to a semiconductor memory device having an electrically floating body. In one conventional technique, a semiconductor memory device having a memory cell with a memory transistor may be read by applying a bias to a drain region of the memory transistor, as well as a bias to a gate of the memory transistor that is above a threshold voltage of the memory transistor. As such, this conventional reading technique may sense an amount of channel current provided/generated in response to the application of the bias to the gate of the memory transistor to determine a state of the memory cell. For example, an electrically floating body region of the memory cell may have two or more different current conditions/states corresponding to two or more different logical states (e.g., two different current conditions/states corresponding to two different logic states: a binary “0” data state and a binary “1” data state).

Also, conventional write techniques for semiconductor memory devices having memory cells with N-Channel type memory transistors typically result in an excess of majority charge carriers in electrically floating body regions of the memory transistors by channel impact ionization or by band-to-band tunneling (gate-induced drain leakage “GIDL”). The majority charge carriers may be removed via drain side hole removal, source side hole removal, or drain and source side hole removal by, for example, using back gate pulsing.

Often, conventional read and write techniques may utilize a large number of voltage drivers (for example, a voltage driver per source line (SL)) which may occupy a large amount of area on a circuit board or die. Also, pulsing between positive and negative gate biases during read and write operations may reduce a net quantity of charge carriers in a body region of a memory cell of a semiconductor memory device, which, in turn, may gradually eliminate data stored in the memory cell. In the event that a negative voltage is applied to a gate of a memory cell transistor, thereby causing a negative gate bias, a channel of minority charge carriers beneath the gate may be eliminated. However, some of the minority charge carriers may remain “trapped” in interface defects. Some of the trapped minority charge carriers may recombine with majority charge carriers, which may be attracted to the gate, and net charge majority charge carriers located in the floating body region may decrease over time. This phenomenon may be characterized as charge pumping, which is a problem because the net quantity of charge carriers may be reduced in the memory cell, which, in turn, may gradually eliminate data stored in the memory cell.

In addition, conventional read and write techniques may utilize multiplexer circuitry to selectively apply one or more bit lines to the input of a sense amplifier. The multiplexer circuitry may add complexity and latency to read and/or write operations. Additionally, the multiplexer circuitry may introduce unwanted capacitance and inductance which may reduce margins of the read and/or write operations.

In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with conventional read and write techniques involving semiconductor memory devices.

SUMMARY OF THE DISCLOSURE

Techniques for reading from and/or writing to a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reading from and/or writing to a semiconductor memory device. The apparatus may comprise a first memory cell array having a first plurality of memory cells arranged in a matrix of rows and columns and a second memory cell array having a second plurality of memory cells arranged in a matrix of row and columns. The apparatus may also comprise a data sense amplifier latch circuitry having a first input node and a second input node. The apparatus may further comprise a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry and a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry.

In accordance with other aspects of this particular exemplary embodiment, wherein the data sense amplifier latch circuitry may further comprise a plurality of transistors arranged in a cross-coupled configuration that may be configured to amplify a voltage or current difference between the first input node and the second input node.

In accordance with further aspects of this particular exemplary embodiment, wherein the first bit line input circuitry may be configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry via a first bit line.

In accordance with additional aspects of this particular exemplary embodiment, wherein the second bit line input circuitry may be configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry via a second bit line.

In accordance with yet another aspect of this particular exemplary embodiment, wherein the first bit line input circuitry may comprise a switch circuitry configured to couple the data sense amplifier latch circuitry to the first memory cell array and a hold circuitry coupled to the first memory cell array to maintain one or more data states stored in the first memory cell array.

In accordance with other aspects of this particular exemplary embodiment, wherein the second bit line input circuitry may comprise a switch circuitry configured to couple the data sense amplifier latch circuitry to the second memory cell array and a hold circuitry coupled to the second memory cell array to maintain one or more data states stored in the second memory cell array.

In accordance with further aspects of this particular exemplary embodiment, the apparatus may further comprise a pre-charge circuitry having a first transistor configured to pre-charge the first input node of the data sense amplifier latch circuitry and a second transistor configured to pre-charge the second input node of the data sense amplifier latch circuitry.

In accordance with additional aspects of this particular exemplary embodiment, the apparatus may further comprise an input/output circuitry coupled to the data sense amplifier latch circuitry configured to output one or more data states of at least one of the first memory cell array and the second memory cell array detected by the data sense amplifier latch circuitry.

In accordance with yet another aspect of this particular exemplary embodiment, wherein the input/output circuitry may comprise a first transistor coupled to the first input node of the data sense amplifier latch circuitry and a second transistor coupled to the second input node of the data sense amplifier latch circuitry.

In accordance with other aspects of this particular exemplary embodiment, the apparatus may further comprise a keeper circuitry coupled to the first bit line input circuitry and the second bit line input circuitry.

In accordance with further aspects of this particular exemplary embodiment, wherein the keeper circuitry may comprise a first transistor coupled to the first bit line input circuitry and the first memory cell array and a second transistor coupled to the second bit line input circuitry and the second memory cell array.

In accordance with additional aspects of this particular exemplary embodiment, the apparatus may further comprise a first writeback circuitry coupled to the first memory cell array and the data sense amplifier latch circuitry.

In accordance with yet another aspect of this particular exemplary embodiment, the apparatus may further comprise a second writeback circuitry coupled to the second memory cell array and the data sense amplifier latch circuitry.

In accordance with other aspects of this particular exemplary embodiment, wherein the first bit line input circuitry may be configured to couple the first memory cell array to the data sense amplifier latch circuitry via a bit line and the second bit line input circuitry may be configured to couple the second memory cell array to the data sense amplifier latch circuitry via the bit line.

In another exemplary embodiment, the techniques may be realized as a method for reading from and/or writing to a semiconductor memory device. The method may comprise arranging a first plurality of memory cells in a matrix of rows and columns in a first memory cell array and a second plurality of memory cells in a matrix of row and columns in a second memory cell array. The method may also comprise coupling the first memory cell array to a first input node of a data sense amplifier latch circuitry via a first bit line input circuitry and coupling the second memory cell array to a second input node of the data sense amplifier latch circuitry via a second bit line input circuitry.

In accordance with other aspects of this particular exemplary embodiment, the method further comprise coupling an input/output circuitry to the data sense amplifier latch circuitry to output one or more data states of at least one of the first memory cell array and the second memory cell array detected by the data sense amplifier latch circuitry.

In accordance with further aspects of this particular exemplary embodiment, the method may further comprise coupling a keeper circuitry to the first bit line input circuitry and the second bit line input circuitry to maintain a voltage at the first bit line input circuitry and a voltage at the second bit line input circuitry within a predetermined range.

In accordance with additional aspects of this particular exemplary embodiment, the method may further comprise coupling a first writeback circuitry to the first memory cell array and the data sense amplifier latch circuitry to perform a write operation.

In accordance with yet another aspect of this particular exemplary embodiment, the method may further comprise coupling a second writeback circuitry to the second memory cell array and the data sense amplifier latch circuitry to perform a write operation.

In accordance with other aspects of this particular exemplary embodiment, wherein coupling the first memory cell array to the first input node of the data sense amplifier latch circuitry via a bit line and coupling the second memory cell array to the second input node of the data sense amplifier latch circuitry via the bit line.

In another particular exemplary embodiment, the techniques may be realized as an apparatus for reading from and/or writing to a semiconductor memory device. The apparatus may comprise a first memory cell array having a first plurality of memory cells arranged in a matrix of rows and columns and a second memory cell array having a second plurality of memory cells arranged in a matrix of row and columns. The apparatus may also comprise a data sense amplifier latch circuitry having a first input node and a second input node. The apparatus may further comprise a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry via a bit line and a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry via the bit line.

In another exemplary embodiment, the techniques may be realized as a method for reading from and/or writing to a semiconductor memory device. The method may comprise arranging a first plurality of memory cells in a matrix of rows and columns in a first memory cell array and a second plurality of memory cells in a matrix of row and columns in a second memory cell array. The method may also comprise coupling the first memory cell array to a first input node of a data sense amplifier latch circuitry via a bit line and coupling the second memory cell array to a second input node of the data sense amplifier latch circuitry via the bit line.

The present disclosure will now be described in more detail with reference to exemplary embodiments thereof as shown in the accompanying drawings. While the present disclosure is described below with reference to exemplary embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present disclosure as described herein, and with respect to which the present disclosure may be of significant utility.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to facilitate a fuller understanding of the present disclosure, reference is now made to the accompanying drawings, in which like elements are referenced with like numerals. These drawings should not be construed as limiting the present disclosure, but are intended to be exemplary only.

FIG. 1A shows a cross-sectional view of a memory cell in accordance with an embodiment of the present disclosure.

FIG. 1B shows a schematic representation of a semiconductor memory device array including a plurality of memory cells arranged in an array of rows and columns in accordance with an embodiment of the present disclosure.

FIGS. 2A and 2B show charge relationships, for given data states, of a memory cell in accordance with embodiments of the present disclosure.

FIG. 3 shows a schematic block diagram of a semiconductor memory device in accordance with an embodiment of the present disclosure.

FIG. 4 shows a schematic block diagram of a portion of a semiconductor memory device 400 in accordance with an embodiment of the present disclosure.

FIG. 5 shows a schematic diagram of data sense circuitry in accordance with an embodiment of the present disclosure.

FIG. 6 shows control signal voltage waveforms for read, write, output, and writeback operations in accordance with an embodiment of the present disclosure.

FIGS. 7A and 7B show data input/output operation control signal voltage waveforms at different timing stages of Write 1, Hold, Read 1, Output, and Write Back in accordance with an embodiment of the present disclosure.

FIGS. 8A and 8B show sense control signal voltage waveforms for performing one or more read operations in accordance with an embodiment of the present disclosure.

FIGS. 9A and 9B show precharge operation timing control signal voltage waveforms in accordance with an embodiment of the present disclosure.

FIGS. 10A and 10B show control signal voltage waveforms for read and write operations in accordance with an embodiment of the present disclosure.

FIGS. 11A and 11B show control signal voltage waveforms for refresh operations in accordance with an embodiment of the present disclosure.

FIG. 12 shows a schematic block diagram of a portion of a semiconductor memory device in accordance with an alternate embodiment of the present invention.

FIG. 13 shows a schematic diagram of data sense circuitry in accordance with an alternate embodiment of the present disclosure.

FIG. 14 shows a schematic diagram of data sense circuitry in accordance with an alternate embodiment of the present disclosure.

FIG. 15 shows a schematic diagram of data sense circuitry in accordance with an alternate embodiment of the present disclosure.

FIGS. 16A, 16B, 16C, and 16D show control signal voltage waveforms for various operations in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

There are many embodiments described and illustrated herein. In a first aspect, the present disclosure is directed to a semiconductor memory device and techniques for reading data from and writing data to memory cells of the semiconductor memory device. In this regard, in one embodiment of this aspect of the present disclosure, techniques are disclosed for reading, writing, sensing, and/or sampling data states from memory cells of the semiconductor memory device.

Referring to FIG. 1A, there is a shown a cross-sectional view of a memory cell 12 in accordance with an embodiment of the present disclosure. The memory cell 12 may comprise a memory transistor 14 (e.g., an N-channel type transistor or a P-channel type transistor) including a gate 16, an electrically floating body region 18, a source region 20, and a drain region 22. An insulating film 17 may be disposed between the gate 16 and the electrically floating body region 18. Moreover, the electrically floating body region 18 may be disposed on or above region 24, which may be an insulation region (e.g., in an SOI material/substrate) or a non-conductive region (e.g., in a bulk-type material/substrate). The insulation or non-conductive region 24 may be disposed on a substrate 26. The electrically floating body region 18 may be disposed between the source region 20 and the drain region 22. Charge carriers 34 may accumulate in or may be emitted/ejected from the electrically floating body region 18. A data state of the memory cell 12 may be defined by an amount of charge carriers 34 present in the electrically floating body region 18.

Referring to FIG. 1B, there is shown a schematic representation of a semiconductor memory device array 10 including a plurality of memory cells 12 arranged in an array of rows and columns in accordance with an embodiment of the present disclosure. The semiconductor memory device array 10 also includes a plurality of word lines (WL) 28, a plurality of source lines (SL) 30, and a plurality of bit lines (BL) 32, each electrically coupled to corresponding ones of the plurality of memory cells 12. Each memory cell 12 may include a memory transistor 14, as described above with reference to FIG. 1A, wherein the source region 20 may be coupled to an associated source line (SL) 30, the drain region 22 may be coupled to an associated bit line (BL) 32, and the gate 16 may be coupled to an associated word line (WL) 28. In an exemplary embodiment, the source region 20 of the memory transistor 14 of each memory cell 12 of a first row of memory cells 12 may be coupled (e.g., via physical diffusion and/or a source line (SL) plane) to a first source line (SL) 30. Also, the source region 20 of the memory transistor 14 of each memory cell 12 of a second row of memory cells 12 may be coupled to the first source line (SL) 30. In another exemplary embodiment, the source region 20 of the memory transistor 14 of each memory cell 12 of a second row of memory cells 12 may be coupled to a second source line (SL) 30, and the source region 20 of the memory transistor 14 of each memory cell 12 of a third row of memory cells may be coupled to a third source line (SL) 30.

Data may be written into a selected memory cell 12 of the semiconductor memory device array 10 by applying suitable control signals to a selected word line (WL) 28, a selected source line (SL) 30, and/or a selected bit line (BL) 32. The memory cell 12 may exhibit (1) a first data state which is representative of a first amount of charge carriers 34 in the electrically floating body region 18 of the memory transistor 14, and (2) a second data state which is representative of a second amount of charge carriers 34 in the electrically floating body region 18 of the memory transistor 14. Additional data states are also possible.

The semiconductor memory device array 10 may further include data write circuitry (not shown), coupled to the selected memory cell 12, to apply (i) first write control signals to the memory cell 12 to write the first data state therein and (ii) second write control signals to the memory cell 12 to write the second data state therein. In response to the first write control signals applied to the selected memory cell 12, the memory transistor 14 may generate a first transistor current which may substantially provide a first amount of charge carriers 34 in the electrically floating body region 18 of the memory transistor 14. In this case, charge carriers 34 may accumulate in or may be emitted/ejected from the electrically floating body region 18. As discussed above, a data state may be defined by an amount of charge carriers 34 present in the electrically floating body region 18. For example, the amount of charge carriers 34 present in the electrically floating body region 18 may represent a logic high (binary “1” data state) or a logic low (binary “0” data state). Additional data states are also possible.

The first write control signals may include a signal applied to the gate 16 and a signal applied to the source region 20, wherein the signal applied to the source region 20 may include a first voltage potential having a first amplitude and a second voltage potential having a second amplitude. In another exemplary embodiment, the first write control signals may include a signal applied to the gate 16 and a signal applied to the drain region 22, wherein the signal applied to the drain region 22 may include a third voltage potential having a third amplitude and a fourth voltage potential having a fourth amplitude.

Also, the second write control signals may include a signal applied to the gate 16, a signal applied to the source region 20, and a signal applied to the drain region 22. The signal applied to the drain region 22 may include a block voltage potential to prevent the first data state from being written into the memory transistor 14.

Referring to FIGS. 2A and 2B, there are shown charge relationships, for given data states, of the memory cell 12 in accordance with exemplary embodiments of the present disclosure. In exemplary embodiments, each memory cell 12 of the semiconductor memory device 10 may operate by accumulating or emitting/ejecting majority charge carriers 34 (e.g., electrons or holes) in/from the electrically floating body region 18. FIGS. 2A and 2B illustrate this with an N-Channel memory transistor 14. More specifically, various write techniques may be employed to accumulate majority charge carriers 34 (in this example, holes) in the electrically floating body region 18 of the memory cell 12 by, for example, impact ionization or hole injection near the source region 20 and/or drain region 22 (see FIG. 2A). Also, the majority charge carriers 34 may be emitted/ejected from the electrically floating body region 18 by, for example, forward biasing a junction between the source region 20 and the electrically floating body region 18 and/or a junction between the drain region 22 and the electrically floating body region 18 (see FIG. 2B).

As shown in FIG. 2A, a logic high (binary “1” data state) may correspond to an increased concentration of majority charge carriers 34 (e.g., holes) in the electrically floating body region 18 relative to an unwritten memory cell 12 and/or a memory cell 12 that is written with a logic low (binary “0” data state). In contrast, as shown in FIG. 2B, a logic low (binary “0” data state) may correspond to a reduced concentration of majority charge carriers 34 (e.g., holes) in the electrically floating body region 18 relative to an unwritten memory cell 12 and/or a memory cell 12 that is written with a logic high (binary “1” data state).

The semiconductor memory device array 10 may further include data sense circuitry (not shown), coupled to the memory cell 12, to sense a data state of the memory cell 12. More specifically, in response to read control signals (first current) applied to the memory cell 12, the memory cell 12 may generate a second transistor current that is representative of a data state of the memory cell 12. The data sense circuitry may determine a data state of the memory cell 12 based at least substantially on the second transistor current (e.g., for a binary “1” data state) or a lack of the second transistor current (e.g., for a binary “0’ data state).

The read control signals may include signals (first current) applied to the gate 16, source region 20, and drain region 22 to cause, force, and/or induce the second transistor current, which is representative of a data state of the memory cell 12. The read control signals applied to the gate 16, source region 20, and drain region 22 may include a positive voltage or a negative voltage. One or more of the read control signals may include a constant or unchanging voltage amplitude.

Referring to FIG. 3, there is shown a schematic block diagram of a semiconductor memory device 300 in accordance with an embodiment of the present disclosure. The semiconductor memory device 300 may include a memory cell array 10, data write and sense circuitry 36, memory cell selection and control circuitry 38, reference current and/or voltage generation circuitry 40, and input/output circuitry 42. The memory cell array 10 may include a plurality of memory cells 12 arranged in a matrix of rows and columns including a plurality of word lines (WL) 28, a plurality of source lines (SL) 30, and a plurality of bit lines (BL) 32. The memory cell array 10 may be coupled to the memory cell selection and control circuitry 38 via the word lines (WL) 28, and/or the source lines (SL) 30. Also, the memory cell array 10 may be coupled to the data write and sense circuitry 36 via the bit lines 32 (BL).

In an exemplary embodiment, the data write and sense circuitry 36 may include a plurality of data sense amplifier circuitry 44 (e.g., 44 a-44 x) and a plurality of reference current and/or voltage input circuitry 46 (e.g., 46 a-46 x). Each data sense amplifier circuitry 44 may receive at least one bit line (BL) 32 and an output of the reference current and/or voltage generator circuitry 40 (for example, a current or voltage reference signal) via a corresponding reference current and/or voltage input circuitry 46. For example, each data sense amplifier circuitry 44 may be a cross-coupled type of sense amplifier to detect, determine, sense, and/or sample a data state of a memory cell 12. Each data sense amplifier circuitry 44 may detect a data state of one or more memory cells 12 (e.g., along bit lines 32 a-32 x (BL)) by comparing voltages or currents on a bit line (BL) 32 with voltages or currents of the output of the reference current and/or voltage generator circuitry 40. Also, each data sense amplifier circuitry 44 may detect a data state of one or more memory cells 12 (e.g., along bit lines 32 a-32 x (BL)) by comparing voltage or current on a bit line (BL) 32 with an unselected pre-charged bit line (BL) voltage or current. For example, the pre-charged bit line (BL) voltage or current may be a hold voltage or current associated with the one or more memory cells in order to retain a data state for a predetermined amount of time. Also, a predetermined voltage may be applied to a bit line 32 (BL) based at least in part on a data state determined by the data sense amplifier circuitry 44 to write-back the data state to one or more memory cells 12. In another exemplary embodiment, predetermined voltages (e.g., voltage data and state) may be applied to a bit line 32 (BL) to write-back a plurality of data states stored in the one or more memory cells 12.

The data sense amplifier circuitry 44 may employ voltage and/or current sensing circuitry and/or techniques. In an exemplary embodiment, the data sense amplifier circuitry 44 may employ current sensing circuitry and/or techniques wherein the data sense amplifier circuitry 44 may compare current from a selected memory cell 12 to a reference current from the reference current and/or voltage input circuitry 46, for example, the current of one or more reference cells. From that comparison, it may be determined whether the memory cell 12 contains a logic high (binary “1” data state, relatively more majority charge carriers 34 contained within the body region 18) or a logic low (binary “0” data state, relatively less majority charge carriers 34 contained within the body region 18). In another exemplary embodiment, the data sense amplifier circuitry may employ voltage sensing circuitry and/or techniques wherein the data sense amplifier circuitry 44 may compare voltage from a selected memory cell 12 to a reference voltage from the reference current and/or voltage input circuitry 46, for example, the voltage of one or more reference cells. From that comparison, it may be determined whether the memory cell 12 contains a logic high (binary “1” data state, relatively more majority charge carriers 34 contained within the body region 18) or a logic low (binary “0” data state, relatively less majority charge carriers 34 contained within the body region 18).

The memory cell selection and control circuitry 38 may select and/or enable one or more predetermined memory cells 12 to facilitate reading data therefrom and/or writing data thereto by applying control signals on one or more word lines (WL) 28 and/or source lines (SL) 30. The memory cell selection and control circuitry 38 may generate such control signals using address signals, for example, row address signals. Moreover, memory cell selection and control circuitry 38 may include a word line decoder and/or driver (not shown). For example, memory cell selection and control circuitry 38 may include one or more different control/selection techniques (and circuitry therefore) to implement memory cell selection techniques. Such techniques, and circuitry therefore, are well known to those skilled in the art. Notably, all such control/selection techniques, and circuitry therefore, whether now known or later developed, are intended to fall within the scope of the present disclosures.

In an exemplary embodiment, the semiconductor memory device 300 may implement a two step write operation whereby selected memory cells 12 of a given row are written to a predetermined data state by first executing a “clear” operation, whereby all of the memory cells 12 of the given row may be written to a logic low (binary “0” data state), and thereafter the selected memory cells 12 of the given row may be selectively written to the predetermined data state (e.g., a logic high (binary “1” data state)). In another exemplary embodiment, selected memory cells 12 of a given row are written to a predetermined data state by first executing a “clear” operation, whereby all of the memory cells 12 of the given row may be written to a logic high (binary “1” data state), and thereafter the selected memory cells 12 of the given row may be selectively written to the predetermined data state (e.g., a logic low (binary “0” data state)). In still another exemplary embodiment, a one step write operation may be implemented, whereby selective memory cells 12 of a given row are selectively written to either a logic high (binary “1” data state) or a logic low (binary “0” data state) without first implementing a “clear” operation.

The semiconductor memory device 300 may employ any of the exemplary writing, holding, and/or reading techniques described herein. Moreover, exemplary voltage values for each of the control signals for a given operation (for example, writing, holding, or reading) may be employed in the semiconductor memory device 300 according to exemplary embodiments of the present disclosure.

The memory transistors 14 may comprise N-channel, P-channel, or a combination of both types of transistors. For example, the memory transistors 12 may be made from an SOI material/substrate or a bulk-type material/substrate. Also, the memory transistors 14 may comprise non-planar transistors, such as, vertical pillar transistors, cylindrical thin-pillar transistors, vertical gated access transistor, fin field effect transistors (FETs), multi-gate field effect transistors (MuGFETs), multiple independent gate field effect transistors (MIGFETs) and/or other multi-gate transistors. In addition, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include P-channel, N-channel type transistors, and/or other devices as discussed above. In the event that P-channel type transistors are employed as memory transistors 14 in the memory cells 12, suitable write and read voltages (for example, negative voltages) may be well known to those skilled in the art in light of this disclosure. Accordingly, for sake of brevity, a discussion of these voltages will not be included herein.

Referring to FIG. 4, there is shown a schematic block diagram of a portion of a semiconductor memory device 400 in accordance with an embodiment of the present disclosure. The semiconductor memory device 400 may include data sense circuitry 402 controllable and/or selectively coupled to one or more memory cell arrays 10 via one or more bit lines 32 (shown in FIG. 3). The data sense circuitry 402 may include one or more bit line input circuitry 404 coupled to each memory cell array 10, data sense amplifier latch circuitry 406, input/output circuitry 408, and/or keeper circuitry 410.

The one or more bit line input circuitry 404 may couple the data sense amplifier latch circuitry 406 to one or more memory cell arrays 10. Also, the one or more bit line input circuitry 404 may apply a hold voltage to the memory cell arrays 10 in order to hold data states (e.g., logic high (binary “1” data state) and logic low (binary “0” data state)) stored in the memory cell arrays 10. In an exemplary embodiment, the one or more bit line input circuitry 404 may include one or more pass gate transistors and/or column switch circuitry to couple the data sense amplifier latch circuitry 406 to the plurality of memory cells 12.

The data sense amplifier latch circuitry 406 may sample, sense, read, and/or determine a logic low (binary “0” data state) or a logic high (binary “1” data state) stored in one or more memory cells 12 (shown in FIG. 3) of one or more memory cell arrays 10. A reference voltage and/or current may be applied to pre-charge the data sense amplifier latch circuitry 406 before a sample, sense, read, and/or data state determining operation. For example, during a sample, sense, read, and/or data state determining operation, the data sense amplifier latch circuitry 406 may compare a current generated by a memory cell 12 with an applied pre-charged reference current. In an exemplary embodiment, the pre-charged reference voltage and/or current applied to the data sense amplifier latch circuitry 406 may have a magnitude between a magnitude of voltage/current that may represent a logic low (binary “0” data state) and a magnitude of voltage/current that may represent a logic high (binary “1” data state) stored in the memory cell 12. In another exemplary embodiment, the pre-charged reference voltage and/or current applied to the data sense amplifier latch circuitry 406 may have a magnitude equal to the magnitude of the voltage/current that may represent a logic low (binary “0” data state) or a magnitude of voltage/current that may represent a logic high (binary “1” data state) stored in the memory cell 12.

The input/output circuitry 408 may allow external access to the plurality of memory cells 12 in the plurality of memory cell arrays 10 via the data sense amplifier latch circuitry 406. The input/output circuitry 408 may selectively and/or controllably output a data state stored in the memory cells 12 of the memory cell arrays 10. Also, the input/output circuitry 408 may selectively and/or controllably input (e.g., write or write-back) a data state to the memory cells 12 of the memory cell arrays 10. In an exemplary embodiment, the input/output circuitry 408 may include pass gates and/or column switch circuitry to facilitate and/or implement various operations on the memory cells 12 of the memory cell arrays 10.

The keeper circuitry 410 may include voltage and/or current stabilizing circuitry coupled to the bit lines (BL) 32 associated with disparate memory cell arrays 10. In an exemplary embodiment, the bit lines (BL) 32 associated with disparate memory cell arrays 10 may have different voltages and/or currents, and the keeper circuitry 410 may maintain the voltages and/or currents on the bit lines (BL) 32 associated with the disparate memory cell arrays 10 within a predetermined range. For example, the keeper circuitry 410 may maintain the voltages and/or current on the bit lines (BL) 32 before, during, and/or after various operations (e.g., sense operation).

The memory cell selection and control circuitry 38 may control one or more selected memory cells 12 of the memory cell arrays 10 coupled to the data sense circuitry 402. In an exemplary embodiment, the memory cell selection and control circuitry 38 may include a plurality of word lines (WL) 28, a plurality of source lines (SL) 30, word line (WL) decoders and/or drivers, and/or source line (SL) decoders and/or drivers. The memory cell selection and control circuitry 38 may apply one or more control signals via the plurality of word lines (WL) 28 and/or the plurality of source lines (SL) 30. Also, the memory cell selection and control circuitry 38 may include pass gates and/or row switch circuitry (not shown) to selectively activate the memory cells 12 in order to perform various operations.

Referring to FIG. 5, there is shown a schematic diagram of data sense circuitry 502 in accordance with an embodiment of the present disclosure. The data sense circuitry 502 may include one or more bit line input circuitry 504 coupled to one or more memory cells 12, data sense amplifier latch circuitry 506, input/output circuitry 508, and/or keeper circuitry 510.

Each bit line input circuitry 504 may include switch circuitry 514 having a pass gate transistor 520 coupling the data sense amplifier latch circuitry 506 to one or more memory cells 12, and hold circuitry 516 having a transistor 522 coupled to one or more memory cells 12 in order to achieve predetermined retention time for a data state stored in the one or more memory cells 12.

The data sense amplifier latch circuitry 506 may include pre-charge circuitry 518 having one or more transistors 524 and 526 for charging the data sense amplifier latch circuitry 506 to a reference voltage and/or current before a sample, sense, read, and/or data state determining operation. Also, the data sense amplifier latch circuitry 506 may include an input node (BPB) coupled to bit line (BLB) 32 and an input node (BP) coupled to a bit line (BL) 32 via the one or more bit line input circuitry 504. In an exemplary embodiment, the input node (BPB) may be set to and/or maintained at a voltage and/or current provided by a memory cell 12 (e.g., FB(0)), while the input node (BP) may be set to and/or maintained at a reference voltage and/or current provided by the pre-charge circuitry 518. In another exemplary embodiment, the input node (BP) may be set to and/or maintained at a voltage and/or current provided by a memory cell 12 (e.g., FB(1)), while the input node (BPB) may be set to and/or maintained at a reference voltage and/or current provided by the pre-charge circuitry 518. The data sense amplifier latch circuitry 506 may determine a data state based on the difference between the voltage or current at the input node (BPB) and the voltage or current at the input node (BP).

The voltage and/or current provided by the memory cell 12 at the input node (BPB) and the reference voltage and/or current provided by the pre-charge circuitry 518 at the input node (BP) may produce a voltage and/or a current differential between the input node (BPB) and the input node (BP). The data sense amplifier latch circuitry 506 may include a plurality of transistors 528-534 arranged in a cross-coupled configuration that may amplify the voltage and/or current difference between the input node (BPB) and the input node (BP).

The pre-charge circuitry 518 may pre-charge a reference node and/or a sense node (e.g., input node BP may be the reference node and then input node BPB may be the sense node or input node BP may be the sense node and then input node BPB may be the reference node). The pre-charge circuitry 518 may pre-charge the reference node and the sense node to the same voltage potential or a different voltage potential. In an exemplary embodiment, the pre-charge circuitry 518 may pre-charge the reference node and the sense node to the same voltage potential. When the pre-charge circuitry 518 pre-charges the reference node and the sense node to the same reference voltage potential, the voltage potential/current detected by the data amplifier latch circuitry 506 from the memory cell 12 may be higher than the reference voltage potential in the event that a logic high (binary “1” data state) is stored in the memory cell 12 or lower than the reference voltage potential in the event that a logic low (binary “0” data state) is stored in the memory cell 12.

In another exemplary embodiment, the pre-charge circuitry 518 may pre-charge the reference node and the sense node to a different voltage potential. The pre-charge circuitry 518 may pre-charge the reference node to a lower voltage potential than the pre-charged voltage potential at the sense node when the data amplifier latch circuitry 506 senses high. The pre-charge circuitry 518 may pre-charge the reference node to a higher voltage potential than the pre-charged voltage potential at the sense node when the data amplifier latch circuitry 506 senses low. In an exemplary embodiment, assuming that a logic high (binary “1” data state) is stored in the memory cell 12. When the data amplifier latch circuitry 506 senses low, the sense node (SN) may be pre-charged to a voltage potential of approximately 0V and the reference node (RN) may be pre-charged to a voltage potential of approximately 100 mV. The logic high (binary “1” data state) stored in the memory cell 12 may cause the voltage potential at the sense node (SN) to rise to approximately 200 mV. The data amplifier latch circuitry 506 may read a logic high (binary “1” data state) is stored in the memory cell 12.

In another exemplary embodiment, assuming that a logic low (binary “0” data state) is stored in the memory cell 12. When the data amplifier latch circuitry 506 senses high, the sense node (SN) may be pre-charged to a voltage potential of approximately VDD voltage potential and the reference node (RN) may be pre-charged to a voltage potential of approximately VDD voltage potential minus 100 mV. The logic low (binary “0” data state) stored in the memory cell 12 may not cause the voltage potential at the sense node to change and the voltage potential at the sense node may maintain at approximately VDD voltage potential. The data amplifier latch circuitry 506 may read a logic low (binary “0” data state) is stored in the memory cell 12. Also, the pre-charged voltage potential at the sense node may change (e.g., rise or fall) to a voltage potential either higher than (e.g., when a logic high (binary “1” data state) is stored in the memory cell 12 and the data amplifier latch circuitry 506 senses low) or below (e.g., when a logic high (binary “1” data state) is stored in the memory cell and the data amplifier latch circuitry 506 senses high) the pre-charged voltage potential at the reference node.

The pre-charged voltage potential at the reference node may be selected based on when the data amplifier latch circuitry 506 senses high or low. For example, the pre-charged voltage potential at the reference node may be selected to be lower than the pre-charged voltage potential at the sense node when the data amplifier latch circuitry 506 senses high. Also, the pre-charged voltage potential at the reference node may be selected to be higher than the pre-charged voltage potential at the sense node when the data amplifier latch circuitry 506 senses low. In an exemplary embodiment, the pre-charged reference voltage at the reference node may be 50 mV lower than the pre-charged voltage potential at the sense node when the data amplifier latch circuitry 506 senses high or 50 mV higher than the pre-charged voltage potential at the sense node when the data amplifier latch circuitry 506 senses low.

In an exemplary embodiment, in the event that a logic high (binary “1” data state) is stored in the memory cell 12, the voltage detected by the data amplifier latch circuitry 506 may be higher than the reference voltage/current when the bit line (BL) 32 is pre-charged to a low voltage (e.g., 0V). In contrast, in the event that a logic high (binary “1” data state) is stored in the memory cell 12, the voltage detected by the data amplifier latch circuitry 506 may be lower than the reference voltage/current when the bit line (BL) 32 is pre-charged to a high voltage (e.g., 2.2V). In another exemplary embodiment, in the event that a logic high (binary “1” data state) is stored in the memory cell 12, the voltage and/or current sunk or provided by the memory cell 12 at the input node (BPB) may be lower or higher than the reference voltage and/or current provided by the pre-charge circuitry 518 at the reference input node (BP). For example, the voltage provided by the memory cell 12 at input node (BPB) may be raised to a threshold voltage (Vt) level and may turn on transistor 532 to “pull” the input node (BP) low and may turn off transistor 534 and may turn on transistor 530. The input node (BPB) may be “pulled” to a voltage potential (e.g., VSL voltage potential) when transistor 536 is turned on via a signal line (SPB). For example, the transistor 530 may not turn on until the transistor 536 is turned on. In other exemplary embodiments, the signal applied via the signal line (SPB) may be pulsed low before the input node (BPB) is switched above a threshold voltage level.

In another exemplary embodiment, in the event that a logic low (binary “0” data state) is stored in the memory cell 12, the voltage and/or current provided by the memory cell 12 at the input node (BPB) may be lower or higher than the reference voltage and/or current provided by the pre-charge circuitry 518 at the reference input node (BP). For example, the voltage provided by the pre-charge circuitry 518 at input node (BP) may be raised to a threshold voltage (Vt) level, and may turn on transistor 534 to “pull” the input node (BPB) low and may turn off transistor 532 and may turn on transistor 528. The input node (BP) may be “pulled” to a voltage potential (e.g., VSL voltage potential) when transistor 536 is turned on via a signal line (SPB). For example, the transistor 528 may not turn on until the transistor 536 is turned on. In other exemplary embodiments, the signal applied via the signal line (SPB) may be pulsed low before the input node (BP) is switched above a threshold voltage level.

The data sense amplifier latch circuitry 506 may sense, sample, and/or determine the data state of a memory cell 12, and store the data state in the data sense amplifier latch circuitry 506. The data state stored in the data sense amplifier latch circuitry 506 may be read or accessed via transistors 538 and 540 of the input/output circuitry 508.

The keeper circuitry 510 may have transistors 542 and 544 coupled to each other and a predetermined voltage source via a signal source line (Keeper). As discussed above, the pre-charge circuitry 518 may pre-charge the input node (BPB) and input node (BP), the keeper circuitry 510 may supply a small amount of current to the input node (BPB) and input node (BP) in order to maintain the pre-charged voltage potential at input node (BPB) and input node (BP). For example, due to leakage effect, charges stored in the electrically floating body region 18 may be depleted via the bit line (BL) 32 and cause a variance in the pre-charged voltage potential at the input node (BPB) and/or input node (BP). By supplying a small amount of current to the input node (BPS) and input node (BP) the variance in the pre-charged voltage potential at the input node (BPS) and/or input node (BP) may be prevented and the pre-charged voltage potential at the input node (BPB) and/or input node (BP) may be maintained. In another exemplary embodiment, in the event that a current of 10 μA is applied at the input node (BPB) and a current of 20 μA is applied at the input node (BP), the voltage at the input node (BP) may be twice the voltage relative to the voltage at the input node (BPB) because twice the current is applied to the input node (BP) as is applied to the input node (BPB).

Referring to FIG. 6, there are shown control signal voltage waveforms for read, write, output, and writeback operations in accordance with an embodiment of the present disclosure. The control signals may be configured to perform a write operation whereby one or more selected memory cells 12 of one or more selected rows of memory cells 12 may be selectively written or programmed to either a logic high (i.e., a binary “1” data state) or a logic low (i.e., a binary “0” date state). As shown in FIG. 6, control signals may be configured to implement a write operation (e.g., logic high (binary “1” data state)) to a memory cells 12 (e.g., a memory cell 12 having a floating body (0) shown in FIG. 5). The temporally varying control signals to implement write a logic high (i.e., a binary “1” data state) operation include a voltage potential applied to the drain region 22 of the memory transistor 14 via the bit line (BL) 32 and/or a voltage potential applied to the gate 16 of the memory transistor 14 via the word line (WL) 28. The logic high (binary “1” data state) may be written to one or more selected memory cells 12 by applying appropriate source line (SL) voltages, word line (WL) voltages, and/or bit line (BL) voltages. For example, the voltage potential applied to the drain region 22 of the memory transistor 14 via the bit line (BL) 32 may raise to a desired predetermined voltage potential level. In an exemplary embodiment, the voltage potential applied to the drain region 22 of the memory transistor 14 via the bit line (BL) 32 may be approximately 2.3V. The input node (BP) of the data sense amplifier latch circuitry 506 may be coupled to the bit line (BL) 32 and the voltage potential at the input node (BP) may raise to the same voltage potential as the bit line (BL) 32. In an exemplary embodiment, the voltage potential at the input node (BP) of the data sense amplifier latch circuitry 506 may be approximately 2.3V.

Also, the voltage potential applied to the gate 16 of the memory transistor 14 may raise to a predetermined voltage potential level. Also, the voltage potential applied to the gate 16 of the memory transistor 14 may vary during a write operation. In an exemplary embodiment, the voltage potential applied to the gate 16 of the memory transistor 14 may initially raise to approximately 0.2V and may subsequently fall to approximately −0.5V. Also, the voltage potential applied to the input node (BPB) of the data sense amplifier latch circuitry 506 may raise to a predetermined voltage potential level. In an exemplary embodiment, the voltage potential at the input node (BPB) of the data sense amplifier latch circuitry 506 may raise to approximately 1.0V. It is preferred that the source voltage potential include an amplitude which may be sufficient to maintain a bipolar current that is suitable for programming the memory cell 12 to a logic high (binary “1” data state). Therefore, majority charge carriers 34 may be generated in the electrically floating body region 18 (e.g., electrically floating body (0) shown in FIG. 5) of the memory transistor 14 via a bipolar current and majority charge carriers 34 may accumulate (and be stored) in a portion of the electrically floating body region 18 of the memory transistor 14 of the memory cell 12 that may be juxtaposed or near the gate dielectric (which is disposed between the gate 16 and the electrically floating body region 18). In an exemplary embodiment, a voltage potential of the floating body region 18 storing the majority charge carriers 34 may be approximately 0.8V.

The control signals may also be configured to perform a read operation whereby one or more selected memory cells 12 of one or more selected rows of memory cells 12 may be selectively read to determine a logic high (i.e., a binary “1” data state) or a logic low (i.e., a binary “0” date state) is stored in the memory cells 12. The voltage potentials on the bit line (BL) 32, the word line (WL) 28, may be raised to a predetermined voltage potential to implement a read operation. As described above, the input node (BP) of the data sense amplifier latch circuitry 506 may be coupled to the bit line (BL) 32 and the voltage potential at the input node (BP) may be raised along with the bit line (BL) 32. Also, the input node (BPB) of the data sense amplifier latch circuitry 506 may be precharged to a predetermined voltage potential level, which may be used as a reference voltage potential to read a data state stored in the memory cell 12. In an exemplary embodiment, the voltage potential on the bit line (BL) 32 and at the input node (BP) of the data sense amplifier latch circuitry 506 may be raised to approximately 2.3V. Also, the input node (BPB) of the data sense amplifier latch circuitry 506 may be precharged to approximately 2.2V. Subsequently, the voltage potential on the word line (WL) 28 may be raised to approximately −0.3V. The voltage potential at the floating body region 18 of the memory cell 12 may be raised to approximately 0.8V and the data sense amplifier latch circuitry 506 may determine a data state stored in the memory cell 12 based at least in part on the voltage potential of the floating body region 18. The data state detected by the data sense amplifier latch circuitry 506 may be outputted via the input/output circuitry 508.

The control signals may also be configured to perform a writeback operation whereby one or more selected memory cells 12 of one or more selected rows of memory cells 12 may be selectively writeback a logic high (i.e., a binary “1” data state) or a logic low (i.e., a binary “0” date state) stored in the memory cells 12. The voltage potentials on the bit line (BL) 32, the word line (WL) 28, may be raised to a predetermined voltage potential to implement a writeback operation. The voltage potentials on the word line (WL) 28 may vary during the writeback operation. As described above, the input node (BP) of the data sense amplifier latch circuitry 506 may be coupled to the bit line (BL) 32 and the voltage potential at the input node (BP) may be raised along with the bit line (BL) 32. Also, the input node (BPB) of the data sense amplifier latch circuitry 506 may be precharged to a predetermined voltage potential level in order to writeback a data state stored in the memory cell 12. In an exemplary embodiment, the voltage potential on the bit line (BL) 32 and at the input node (BP) of the data sense amplifier latch circuitry 506 may be raised to approximately 1.2V. Also, the input node (BPB) of the data sense amplifier latch circuitry 506 may be precharged to approximately 2.3V. Subsequently, the voltage potential on the word line (WL) 28 may be raised to approximately 0.3V and lowered to −0.5V at a later time during the writeback operation. The voltage potential at the floating body region 18 of the memory cell 12 may be raised to approximately 0.6V to approximately −0.1V and the data state detected by the data sense amplifier latch circuitry 506 may be writeback to the memory cell 12.

Referring to FIGS. 7A and 7B, there are shown data input/output operation control signal voltage waveforms at different timing stages of Write 1, Hold, Read 1, Output, and Write Back in accordance with an embodiment of the present disclosure. The data stored in the data sense amplifier latch circuitry 506 may be read or accessed via transistors 538 and 540 of the input/output circuitry 508. The a voltage potential (IOB) may be applied to the transistor 538 and a voltage potential (IO) may be applied to the transistor 540 in order to output a data state detected by the data sense amplifier latch circuitry 506. The voltage potential (IO) applied to the transistor 540 may be raised during a write, a hold, and a read operation to properly bias the transistor 540. Also, the voltage potential (IOB) applied to the transistor 538 may be lower during a write, a hold, and a read operation to properly bias the transistor 540. In an exemplary embodiment, the voltage potential (IO) may be raised to approximately 2.3V during a write, a hold, and a read operation. During an output operation, the voltage potential (IO) applied to the transistor 540 may be lowered, while the voltage potential (IOB) applied to the transistor 538 may be raised. In an exemplary embodiment, the voltage potential (IO) applied to the transistor 540 may be lowered to approximately 1V, while the voltage potential (IOB) applied to the transistor 538 may be raised to approximately 2.3V. Also, during a writeback operation, the voltage potential (IO) applied to the transistor 540 may be raised and the voltage potential (IOB) applied to the transistor 538 may be lowered. In an exemplary embodiment, the voltage potential (IO) applied to the transistor 540 may be raised to approximately 1.6V and the voltage potential (IOB) applied to the transistor 538 may be lowered to approximately 2V.

Also, shown in FIG. 7B, during the write operation, read operation, output operation, and the writeback operation, the voltage potentials on the word line (WL) 28 and at the input nodes (BP) and (BPB) of the data sense amplifier latch circuitry 506 may be similar to the voltage potentials illustrated in FIG. 6, as described above. A voltage potential (RWB) may be applied to the gate 16 of the transistors 538 and 540 in order to control an operation of the transistors 538 and 540. As shown in FIG. 7B, the voltage potential (RWB) applied to the gate 16 of the transistor 538 and 540 may be lowered during a write operation and/or an output operation. In an exemplary embodiment, the voltage potential (RWB) applied to the gate 16 of the transistors 538 and 540 may be lowered to approximately 1.1V during a write operation and/or an output operation.

Referring to FIGS. 8A and 8B, there are shown sense control signal voltage waveforms for performing one or more read operations in accordance with an embodiment of the present disclosure. For example, one or more read operations may include a read logic low (binary “0” data state) operation and/or a read logic high (binary “1” data state) operation. The voltage potentials applied to the data sense circuitry 502 (shown in FIG. 5) may be different for a read logic low (binary “0” data state) operation and a read logic high (binary “1” data state) operation. Each of the read logic low (binary “0” data state) and the read logic high (binary “1” data state) may be divided into one or more segments. For example, each of the read logic low (binary “0” data state) and the read logic high (binary “1” data state) may include a precharge segment, a signal development segment, and/or an isolate and sense segment.

During a reading logic low (binary “0” data state), input nodes (BP) and (BPB) of the data sense amplifier latch circuitry 506 may be precharged to a predetermined voltage potential level during the precharge segment. In an exemplary embodiment, the input node (BP) (e.g., reference node) of the data sense amplifier latch circuitry 506 may be precharged to a voltage potential of approximately 2.2V and the input node (BPB) (e.g., sense node) of the data sense amplifier latch circuitry 506 may be precharged to a voltage potential of approximately 2.3V. As discussed above, the input nodes of the data sense amplifier latch circuitry 506 may be precharged by the precharge circuitry 518. For example, the input node (BP) of the data sense amplifier latch circuitry 506 may be precharged to a predetermined voltage potential level via the transistor 526. The input node (BPB) of the data sense amplifier latch circuitry 506 may be precharged to a predetermined voltage potential level via the transistor 524. A voltage potential (VALBB) may be applied the transistor 524 in order to precharge the input node (BPB) of the data sense amplifier latch circuitry 506. A voltage potential (VALB) may be applied to the transistor 526 in order to precharge the input node (BP) of the data sense amplifier latch circuitry 506. In an exemplary embodiment, during the precharge segment of a read logic low (binary “0” data state), a voltage potential (VALBB) applied to the transistor 524 may be raised to approximately 2.3V from 2.2V and a voltage potential (VALB) applied to the transistor 526 may be lowered to approximately 2.2V from 2.3V.

During a signal development segment of a read logic low (binary “0” data state”) operation, a voltage potential at input nodes (BP) and (BPB) of the data sense amplifier latch circuitry 506 may remain the same as the voltage potential during the precharge segment. In an exemplary embodiment, a voltage potential at the input node (BPB) of the data sense amplifier latch circuitry 506 may remain at approximately 2.3V and a voltage potential at the input node (BP) of the data sense amplifier latch circuitry 506 may remain at approximately 2.2V. Also, the voltage potential (VALB) and the voltage potential (VALBB) during the signal development segment may remain the same as during the precharge segment of the read logic low (binary “0” data state) operation. In an exemplary embodiment, a voltage potential (VALB) applied to the transistor 526 may remain at approximately 2.2V and a voltage potential (VALBB) applied to the transistor 524 may remain at approximately 2.3V.

During the isolate and sense segment of a read logic low (binary “0” data state) operation, the voltage potential at the input node (BP) of the data sense amplifier latch circuitry 506 may be lowered while the voltage potential at the input node (BPB) of the data sense amplifier latch circuitry 506 may remain constant. In an exemplary embodiment, the voltage potential at the input node (BP) of the data sense amplifier latch circuitry 506 may be lowered to approximately 1.1V from 2.3V while the voltage potential at the input node (BPB) of the data sense amplifier latch circuitry 506 may remain constant at approximately 2.3V. Also, the voltage potential (VALB) applied to the transistor 526 and the voltage potential (VALBB) applied to the transistor 524 may remain constant. In an exemplary embodiment, the voltage potential (VALB) applied to the transistor 526 may remain constant at approximately 2.2V and the voltage potential (VALBB) applied to the transistor 524 may remain constant at approximately 2.3V.

During a reading logic high (binary “1” data state), input nodes (BP) (e.g., sense node) and input node (BPB) (e.g., reference node) of the data sense amplifier latch circuitry 506 may be precharged to a predetermined voltage potential level during the precharge segment. In an exemplary embodiment, the input node (BP) of the data sense amplifier latch circuitry 506 may be precharged to a voltage potential of approximately 2.3V and the input node (BPB) of the data sense amplifier latch circuitry 506 may be precharged to a voltage potential of approximately 2.2V. As discussed above, the input nodes of the data sense amplifier latch circuitry 506 may be precharged by the precharge circuitry 518 comprising transistors 524 and 526. For example, the input node (BP) of the data sense amplifier latch circuitry 506 may be precharged to a predetermined voltage potential level via the transistor 526. The input node (BPB) of the data sense amplifier latch circuitry 506 may be precharged to a predetermined voltage potential level via the transistor 524. A voltage potential (VALBB) may be applied the transistor 524 in order to precharge the input node (BPB) of the data sense amplifier latch circuitry 506. A voltage potential (VALB) may be applied to the transistor 526 in order to precharge the input node (BP) of the data sense amplifier latch circuitry 506. In an exemplary embodiment, during the precharge segment of a read logic high (binary “1” data state), a voltage potential (VALBB) applied to the transistor 524 may be lowered to approximately 2.2V from 2.3V and a voltage potential (VALB) applied to the transistor 526 may be raised to approximately 2.3V from 2.2V.

During a signal development segment of a read logic high (binary “1” data state”) operation, a voltage potential at input nodes (BP) and (BPB) of the data sense amplifier latch circuitry 506 may not remain the same as the voltage potential during the precharge segment. In an exemplary embodiment, a voltage potential at the input node (BP) of the data sense amplifier latch circuitry 506 may be pulled low to approximately 2.1V by the voltage and/or current generated by the memory cell 12 and a voltage potential at the input node (BPB) of the data sense amplifier latch circuitry 506 may remain at approximately 2.2V. Also, the voltage potential (VALB) and the voltage potential (VALBB) during the signal development segment may remain the same as during the precharge segment of the read logic high (binary “1” data state) operation. In an exemplary embodiment, a voltage potential (VALB) applied to the transistor 526 may remain at approximately 2.3V and a voltage potential (VALBB) applied to the transistor 524 may remain at approximately 2.2V.

During the isolate and sense segment of a read logic high (binary “1” data state) operation, the voltage potential at the input node (BP) of the data sense amplifier latch circuitry 506 may be lowered while the voltage potential at the input node (BPB) of the data sense amplifier latch circuitry 506 may remain constant. In an exemplary embodiment, the voltage potential at the input node (BP) of the data sense amplifier latch circuitry 506 may be lowered to approximately 1.1V from 2.3V while the voltage potential at the input node (BPB) of the data sense amplifier latch circuitry 506 may remain constant at approximately 2.2V. Also, the voltage potential (VALB) applied to the transistor 526 and the voltage potential (VALBB) applied to the transistor 524 may remain constant. In an exemplary embodiment, the voltage potential (VALB) applied to the transistor 526 may remain constant at approximately 2.3V and the voltage potential (VALBB) applied to the transistor 524 may remain constant at approximately 2.2V.

The data sense amplifier latch circuitry 506 may detect data states of a plurality of memory cells 12 (e.g., memory cell (FB(0) and memory cell (FB(1)). The input node (BP) of the data sense amplifier latch circuitry 506 may be coupled to a memory cell 12 via a bit line (BL) 32 and the input node (BPB) of the data sense amplifier latch circuitry 506 may be coupled to a memory cell 12 via a bit line (BLB) 32. A read logic low (binary “0” data state) operation or a read logic high (binary “1” data state) operation may be performed for the memory cells via the bit line (BL) 32 or the bit line (BLB) 32. As illustrated in FIG. 8B, a read logic low (binary “0” data state) operation may be performed for the memory cell 12 coupled to the bit line (BLB) 32 and a read logic high (binary “1” data state) operation may be performed for the memory cell 12 coupled to the bit line (BL) 32. In an exemplary embodiment, a voltage potential on the bit line (BLB) 32 may be raised to approximately 2.3V from 0V, during a read logic low (binary “0” data state) and a voltage potential on the bit line (BL) 32 may be raised to approximately 2.3V from 0V, during a read logic high (binary “1” data state).

As discussed above, the data sense amplifier latch circuitry 506 may detect data states of a plurality of memory cells 12. The data sense amplifier latch circuitry 506 may select to detect data states of memory cells 12 via the plurality of switch circuitries 514. A voltage potential (PASS1) may be applied to a first switch circuitry 514 and a second voltage potential (PASS2) may be applied to a second switch circuitry 514 in order to couple the memory cells 12 to the data sense amplifier latch circuitry 506. In an exemplary embodiment, a voltage potential (PASS2) may remain low (e.g., approximately 0V) during a precharge segment and/or a signal development segment of a read logic low (binary “0” data state). Subsequently, the voltage potential (PASS2) may raise to approximately 2.3V from 0V during the isolation and sense segment of the read logic low (binary “0” data state) operation. Also, a voltage potential (PASS1) may remain constant at approximately 2.3V during a read logic low (binary “0” data state). In another exemplary embodiment, a voltage potential (PASS2) may remain constant at approximately 2.3V. A voltage potential (PASS1) may be lowered to approximately 0V from 2.3V during the precharge segment and/or the signal development segment of the read logic high (binary “1” data state) operation. The voltage potential (PASS1) may be raised to approximately 2.3V from 0V, during the isolate and sense segment of a read logic high (binary “1” data state) operation.

One or more voltage potentials may be applied to the data sense amplifier latch circuitry 506 in order to perform a read logic low (binary “0” data state) operation and/or a read logic high (binary “0” data state) operation. For example, a voltage potential (SPB) may be applied to the transistor 536 of the data sense amplifier latch circuitry 506 to control a voltage potential at the transistors 528 and 530. A voltage potential (SN) may be applied to the data sense amplifier latch circuitry 506 to control a voltage potential at the transistors 532 and 534. The voltage potential (SPB) and the voltage potential (SN) applied to the data sense amplifier latch circuitry 506 may be similar during a read logic low (binary “0” data state) operation. In an exemplary embodiment, a voltage potential (SPB) applied to the data sense amplifier latch circuitry 506 may remain high (e.g., at approximately 2.3V) during the precharge segment and/or the signal development segment of a read logic low (binary “0” data state) operation. The voltage potential (SPB) may be lowered to approximately 1V from 2.3V during the isolate and sense segment of a read logic low (binary “0” data state) operation. A voltage potential (SN) may be configured in a similar manner as the voltage potential (SPB) during a read logic low (binary “0” data state) operation.

During a read logic high (binary “1” data state) operation, a voltage potential (SPB) may remain high during the precharge segment and/or the signal development segment and may be lowered during the isolate and sense segment. Also, a voltage potential (SN) may be configured in a similar manner as the voltage potential (SPB) during a read logic high (binary “1” data state) operation. In an exemplary embodiment, a voltage potential (SPB) applied to the data sense amplifier latch circuitry 506 may be approximately 2.3V during the precharge segment and/or the signal development segment of a read logic high (binary “1” data state) operation. The voltage potential (SPB) may be lowered to approximately 1V from 2.3V during the isolate and sense segment of the read logic high (binary “1” data state) operation. The voltage potential (SN) may be configured in a similar manner as the voltage potential (SPB) during the read logic high (binary “1” data state) operation.

As discussed above, the input node (BP) and the input node (BPB) of the data sense amplifier latch circuitry 506 may be precharged by the precharge circuitry 518. A voltage potential (PCHBB) may be applied to the transistor 524 of the precharge circuitry 518 to bias the input node (BPB) of the data sense amplifier latch circuitry 506. A voltage potential (PCHB) may be applied to the transistor 526 of the precharge circuitry 518 to bias the input node (BP) of the data sense amplifier latch circuitry 506. During a read logic low (binary “0” data state) operation, the voltage potential (PCHBB) and the voltage potential (PCHB) may be varied to bias the input nodes (BPB) and (BP) of the data sense amplifier latch circuitry 506. In an exemplary embodiment, a voltage potential (PCHBB) may be lowered to approximately 1V from 2.3V, during the precharge segment of a read logic low (binary “0” data state) operation. The voltage potential (PCHBB) may be raised to approximately 2.3V from 1V, during the signal development segment and/or the isolate and sense segment of the read logic low (binary “0” data state) operation. A voltage potential (PCHB) may be lowered to approximately 1V from 2.3V, during the precharge segment and/or the signal development segment of a read logic low (binary “0” data state) operation. The voltage potential (PCHB) may be raised to approximately 2.3V from 1V, during the isolate and sense segment of the read logic low (binary “0” data state) operation.

In another exemplary embodiment, a voltage potential (PCHBB) may be lowered to approximately 1V from 2.3V, during the precharge segment and/or the signal development segment of a read logic high (binary “1” data state) operation. The voltage potential (PCHBB) may be raised to approximately 2.3V from 1V, during the isolate and sense segment of the read logic high (binary “1” data state) operation. A voltage potential (PCHB) may be lowered to approximately 1V from 2.3V, during the precharge segment of a read logic high (binary “1” data state) operation. The voltage potential (PCHB) may be raised to approximately 2.3V from 1V, during the signal development segment and/or the isolate and sense segment of the read logic high (binary “1” data state) operation.

Referring to FIGS. 9A and 9B, there are shown precharge operation timing control signal voltage waveforms in accordance with an embodiment of the present disclosure. An exemplary precharge operation may follow a write operation and follow by a read operation. As illustrated in FIGS. 9A and 9B, the precharge operation may begin at approximately 151 nanoseconds and may end at approximately 181 nanoseconds. During a precharge operation, a voltage potential (HLD) applied to the hold circuitry 516 having a transistor 522 may be varied. For example, the voltage potential (HLD) applied to the hold circuitry 516 may raise to 1V from 0V for approximately 10 ns. Subsequently, the voltage potential (HLD) may fall back down to 0V for the remainder of the precharge operation. The change in the voltage potential (HLD) may cause a corresponding change in the bit line (BL) and (BLB) voltage potentials. For example, a raise in the voltage potential (HLD) for the hold circuitry 516 may cause a corresponding fall in the bit line (BL) and (BLB) voltage potential. In an exemplary embodiment, the raise in the voltage potential (HLD) for the hold circuitry 516 may cause the bit line (BL) voltage potential to fall to approximately 0V from 2.3V. The bit line (BL) voltage potential may remain at 0V for the remainder of the precharge operation. The voltage potential at the input node (BP) may fall corresponding to the fall in the bit line (BL) voltage potential. In an exemplary embodiment, the fall of the bit line (BL) voltage potential may cause the voltage potential at the input node (BP) of the data sense amplifier latch circuitry 506 to fall to approximately 0.5V from 2.3V.

As discussed above, the data sense amplifier latch circuitry 506 may be precharged by the precharge circuitry 518. Also, a voltage potential (VSL) may be applied to the data sense amplifier latch circuitry 506 during the precharge operation. In an exemplary embodiment, the voltage potential (VSL) applied to the data sense amplifier latch circuitry 506 may be approximately 2.3V for the duration of the precharge operation. The precharge circuitry 518 may comprise transistors 524 and 526. The transistor 524 may precharge the first input node (BPB) of the data sense amplifier latch circuitry 506 and the transistor 526 may precharge the second input node (BP) of the data sense amplifier latch circuitry 506. A voltage potential (PCHBB) may be applied to the gate 16 of the transistor 524 and a voltage potential (VALBB) may be applied to the source region 20 of the transistor 524. The voltage potential (VALBB) (e.g., shown in FIG. 9B) may raise first followed by a fall in the voltage potential (PCHBB) during the precharge operation to properly bias the transistor 524.

In an exemplary embodiment, the voltage potential (VALBB) may start to raise at approximately 168 ns to approximately 2.3V from 2.2V. Subsequently, the voltage potential (PCHBB) may start to fall at approximately 171 ns to approximately 1.1V from 2.3V. In other exemplary embodiments, a voltage potential (PCHB) may be applied to the gate 16 of the transistor 526 and a voltage potential (VALB) may be applied to the source region 20 of the transistor 526. The voltage potential (VALB) (e.g., shown in FIG. 9B) may fall first follow by a fall in the voltage potential (PCHB) during the precharge operation to properly bias the transistor 526. In an exemplary embodiment, the voltage potential (VALB) may start to fall at approximately 168 ns to approximately 2.2V from 2.3V. Subsequently, the voltage potential (PCHB) may start to fall at approximately 171 ns to approximately 1.1V from 2.3V.

After applying proper voltage potential to the transistors 524 and 526 of the precharge circuitry 516, the first input nodes (BP) and the second input node (BPB) of the data sense amplifier latch circuitry 506 may be properly precharged. In an exemplary embodiment, the voltage potential at the first input node (BP) of the data sense amplifier latch circuitry 506 may be precharged to approximately 2.2V from 0.5V and the voltage potential at the second input node (BPB) of the data sense amplifier latch circuitry 506 may be precharged to approximately 2.3V from 0.5V. The raise in the voltage potential at the input node (BPB) of the data sense amplifier latch circuitry 506 may cause a corresponding raise in voltage potential on the bit line (BLB). In an exemplary embodiment, the raise in the voltage potential at the input node (BPB) of the data sense amplifier latch circuitry 506 may cause the voltage potential on the bit line (BLB) to raise to approximately 2.3V from 0V.

As illustrated in FIG. 9B, the voltage potential on the word line (WL) 28 may vary to properly bias the memory cell 12 during the precharge operation. In an exemplary embodiment, the voltage potential on the word line (WL) 28 may start to fall at approximately 165 ns to approximately −1.5V from −0.5V.

Referring to FIGS. 10A and 10B, there are shown control signal voltage waveforms for read and write operations in accordance with an embodiment of the present disclosure. One or more read operations may be performed wherein the data sense amplifier latch circuitry 506 may detect one or more data states stored in the memory cells 12. As illustrated in FIG. 10A, a first read operation (Read 1) may be performed follow by a first write operation (Write 1) for a memory cell 12. Also, a second read operation (Read 2) may be performed follow by a second write operation (Write 2) for another memory cell 12. During a first read operation, a word line (WL) 28 associated with a first memory cell 12 may remain inactive while a word line (WL) 28 associated with a second memory cell 12 may vary to bias the second memory cell 12 for the read operation. In an exemplary embodiment, a voltage potential (WL(1)) on the word line (WL) 28 associated with a first memory cell 12 may remain constant at approximately −1.5V. A voltage potential (WL(2)) on the word line (WL) 28 associated with a second memory cell 12 may raise from approximately −1.5V to −0.075V for 4 ns before fall back down to approximately −1.5V during the read operation. During a second read operation, a word line (WL) 28 associated with a first memory cell 12 may vary to bias the first memory cell 12 for the read operation while a word line (WL) 28 associated with a second memory cell 12 may remain inactive. In an exemplary embodiment, a voltage potential (WL(1)) on the word line (WL) 28 associated with a first memory cell 12 may raise from approximately −1.5V to −0.075V for 4 ns before fall back down to approximately −1.5V during the read operation. A voltage potential (WL(2)) on the word line (WL) 28 associated with a second memory cell 12 may remain constant at approximately −1.5V.

During the first read operation (Read 1), a voltage potential (HLD) applied to the hold circuitry 516 may remain constant. In an exemplary embodiment, the voltage potential (HLD) may remain at approximately 0V during a first read operation. The voltage potential (HLD) applied during the second read operation (Read 2) may vary. In an exemplary embodiment, the voltage potential (HLD) may fall to approximately 0V from 1.1V during the second read operation (Read 2).

During a read operation, different voltage potentials may be applied to the precharge circuitry 518. A voltage potential (VALBB) may be applied to the source region 20 of the transistor 524 and a voltage potential (PCHBB) may be applied to the gate 16 of the transistor 524. For example, during the first read operation (Read 1) the voltage potential (VALBB) may remain constant, while the voltage potential (PCHBB) may vary during the read operation. In an exemplary embodiment, the voltage potential (VALBB) may remain at approximately 2.3V, while the voltage potential (PCHBB) may increase from approximately 1.2V to 2.3V. Also, a voltage potential (VALB) may be applied to the source region 20 of the transistor 526 and a voltage potential (PCHB) may be applied to the gate 16 of the transistor 526. The voltage potential (VALB) may remain constant, while the voltage potential (PCHB) may vary during the read operation. In an exemplary embodiment, the voltage potential (VALB) may remain at approximately 2.2V, while the voltage potential (PCHB) may increase from approximately 1.2V to 2.3V.

During the second read operation (Read 2) the voltage potential (VALBB) may remain constant, while the voltage potential (PCHBB) may vary during the read operation. In an exemplary embodiment, the voltage potential (VALBB) may remain at approximately 2.2V, while the voltage potential (PCHBB) may fall to approximately 1.2V from 2.3V for approximately 20 ns before raise back to approximately 2.3V. Also, the voltage potential (VALB) may remain constant, while the voltage potential (PCHB) may vary during the second read operation (Read 2). In an exemplary embodiment, the voltage potential (VALB) may remain at approximately 2.3V, while the voltage potential (PCHB) may fall to approximately 1.2V from 2.3V for approximately 15 ns before raise back to approximately 2.3V.

Also, various voltage potentials may be applied to the data sense amplifier latch circuitry 506 during a read operation. For example, a voltage potential (VSL) may be applied to the source region 20 of the transistor 536 and a voltage potential (SPD) may be applied to the gate 16 of the transistor 536. The voltages potentials (VSL) and (SPD) may properly bias the transistor 536 of the data sense amplifier latch circuitry 506 for a read operation. The voltage potential (VSL) may remain constant during one or more read operations (e.g., first read operation (Read 1) and a second read operation (Read 2)). In an exemplary embodiment, the voltage potential (VSL) may remain approximately 2.3V during the first read operation (Read 1) and the second read operation (Read 2). The voltage potential (SPD) may vary during a read operation. In an exemplary embodiment, the voltage potential (SPD) may fall from approximately 2.3V to approximately 1.1V during a first read operation (Read 1) and/or a second read operation (Read 2). Another voltage potential (SN) may be applied to the transistors 532 and 534 of the data sense amplifier latch circuitry 506. The voltage potential (SN) applied to the transistors 532 and 534 may vary during a read operation. In an exemplary embodiment, the voltage potential (SN) may fall from approximately 2.3V to approximately 1.1V during a first read operation (Read 1) and/or a second read operation (Read 2).

During a read operation, switch circuitry 514 may be biased in order to couple the data sense amplifier latch circuitry 506 to one or more memory cells 12. During a first read operation (Read 1), a first voltage potential (PASS1) applied to the first switch circuitry 514 may remain constant while a second voltage potential (PASS 2) applied to the second switch circuitry 514 may vary. In an exemplary embodiment, the first voltage potential (PASS1) applied to the first switch circuitry 514 may remain at approximately 2.3V during a first read operation. The second voltage potential (PASS 2) applied to the second switch circuitry 514 may raise to approximately 2.3V from 0V for approximately 5 ns before fall back down to 0V.

During a second read operation (Read 2), the first voltage potential (PASS1) applied to the first switch circuitry 514 may vary while a second voltage potential (PASS 2) applied to the second switch circuitry 514 may remain constant. In an exemplary embodiment, the first voltage potential (PASS1) applied to the first switch circuitry 514 may fall to approximately 0V from 2.3V and raise to approximately 2.3V from 0V for approximately 5 ns before fall back down to 0V. The second voltage potential (PASS 2) applied to the second switch circuitry 514 may remain at approximately 2.3V during a second read operation (Read 2).

One or more write operations may be performed wherein the data sense amplifier latch circuitry 506 may write one or more data states (e.g., logic low (binary “0” data state) and/or logic high (binary “1” data state)) to the memory cells 12. During a first read operation, a word line (WL) 28 associated with a first memory cell 12 may remain inactive while a word line (WL) 28 associated with a second memory cell 12 may vary to bias the second memory cell 12 for the write operation. In an exemplary embodiment, a voltage potential (WL(1)) on the word line (WL) 28 associated with a first memory cell 12 may remain constant at approximately −1.5V. A voltage potential (WL(2)) on the word line (WL) 28 associated with a second memory cell 12 may raise from approximately −1.5V to 0.0V for approximately 4 ns before fall down to approximately −0.5V for approximately 10 ns and back down to approximately −1.5V. During a second write operation, a word line (WL) 28 associated with a first memory cell 12 may vary to bias the first memory cell 12 for the write operation while a word line (WL) 28 associated with a second memory cell 12 may remain inactive. In an exemplary embodiment, a voltage potential (WL(1)) on the word line (WL) 28 associated with a first memory cell 12 may raise from approximately −1.5V to 0.0V for approximately 4 ns before fall back down to approximately −0.5V for approximately 10 ns and back down to approximately −1.5V. A voltage potential (WL(2)) on the word line (WL) 28 associated with a second memory cell 12 may remain constant at approximately −1.5V during the second write operation.

During the first write operation (Write 1), a voltage potential (HLD) applied to the hold circuitry 516 may vary. In an exemplary embodiment, the voltage potential (HLD) may raise to approximately 2.3V from 0.0V during a first write operation. The voltage potential (HLD) applied during the second write operation (Write 2) may vary in a similar manner as the first write operation. In an exemplary embodiment, the voltage potential (HLD) may raise to approximately 2.3V from 0.0V during the second write operation (Write 2).

During a write operation, different voltage potentials may be applied to the precharge circuitry 518. A voltage potential (VALBB) may be applied to the source region 20 of the transistor 524 and a voltage potential (PCHBB) may be applied to the gate 16 of the transistor 524. For example, during the first write operation (Write 1), the voltage potential (VALBB) and the voltage potential (PCHBB) may remain constant during the read operation. In an exemplary embodiment, the voltage potential (VALBB) may remain at approximately 2.3V and the voltage potential (PCHBB) may remain at approximately 2.3V. Also, a voltage potential (VALB) may be applied to the source region 20 of the transistor 526 and a voltage potential (PCHB) may be applied to the gate 16 of the transistor 526. The voltage potential (VALB) and the voltage potential (PCHB) may remain constant during the first write operation. In an exemplary embodiment, the voltage potential (VALB) may remain at approximately 2.2V and the voltage potential (PCHB) may remain at approximately 2.3V.

During the second write operation (Write 2) the voltage potential (VALBB) and the voltage potential (PCHBB) may remain constant during the second write operation. In an exemplary embodiment, the voltage potential (VALBB) may remain at approximately 2.2V and the voltage potential (PCHBB) may remain at approximately 2.3V. Also, the voltage potential (VALB) and the voltage potential (PCHB) may remain constant during the second write operation (Write 2). In an exemplary embodiment, the voltage potential (VALB) may remain at approximately 2.3V and the voltage potential (PCHB) may remain at approximately 2.3V.

Also, various voltage potentials may be applied to the data sense amplifier latch circuitry 506 during a write operation. For example, a voltage potential (VSL) may be applied to the source region 20 of the transistor 536 and a voltage potential (SPD) may be applied to the gate 16 of the transistor 536. The voltages potentials (VSL) and (SPD) may properly bias the transistor 536 of the data sense amplifier latch circuitry 506 for a write operation. The voltage potential (VSL) may remain constant during one or more write operations (e.g., first write operation (Write 1) and a second write operation (Write 2)). In an exemplary embodiment, the voltage potential (VSL) may remain at approximately 2.3V during the first write operation (Write 1) and the second write operation (Write 2). The voltage potential (SPD) may vary during a write operation. In an exemplary embodiment, the voltage potential (SPD) may raise from approximately 1.1V to approximately 2.3V during a first write operation (write 1) and/or a second write operation (Write 2). Another voltage potential (SN) may be applied to the transistors 532 and 534 of the data sense amplifier latch circuitry 506. The voltage potential (SN) applied to the transistors 532 and 534 may vary during a write operation. In an exemplary embodiment, the voltage potential (SN) may raise from approximately 1.1V to approximately 2.3V during a first write operation (Write 1) and/or a second write operation (Write 2).

During a write operation, switch circuitry 514 may be biased in order to couple the data sense amplifier latch circuitry 506 to one or more memory cells 12. During a first write operation (Write 1), a first voltage potential (PASS1) applied to the first switch circuitry 514 may remain constant while a second voltage potential (PASS 2) applied to the second switch circuitry 514 may vary. In an exemplary embodiment, the first voltage potential (PASS1) applied to the first switch circuitry 514 may remain at approximately 2.3V during a first write operation (Write 1). The second voltage potential (PASS 2) applied to the second switch circuitry 514 may raise to approximately 2.3V from 0V.

During a second write operation (Write 2), the first voltage potential (PASS1) applied to the first switch circuitry 514 and a second voltage potential (PASS 2) applied to the second switch circuitry 514 may remain constant. In an exemplary embodiment, the first voltage potential (PASS1) applied to the first switch circuitry 514 may remain at approximately 0V. The second voltage potential (PASS 2) applied to the second switch circuitry 514 may remain at approximately 2.3V during a second write operation (Write 2).

Referring to FIGS. 11A and 11B, there are shown control signal voltage waveforms for refresh operations in accordance with an embodiment of the present disclosure. The control signals may be configured to perform a number of read operations and write operations whereby one or more selected memory cells of one or more selected rows of memory cells 12 may be selectively refreshed. As shown in FIGS. 11A and 11B, the temporally varying control signals to implement four read operations and four write operations including voltage potentials applied to the drain region 22 of the first memory transistor 14 via the bit line (BL) 32 and/or a voltage potential applied to the gate 16 of the first memory transistors 14 via the word line (WL(2)) 28. During a first read operation (Read 1), a data state stored in the electrically floating body region 18 (e.g., FB(1)) of the first memory transistor 14 may be read by applying a voltage potential applied to the drain region 22 of a first memory transistor 14 via the bit line (BL) 32. In an exemplary embodiment, the voltage potential applied to the drain region 22 of a first memory transistor 14 via the bit line (BL) 32 may fall to approximately 2.0V from 2.3V (Read 1). Also, a voltage potential applied to a first memory transistor 14 via a first word line (WL(2)) 28 may vary. In an exemplary embodiment, the voltage potential applied to the gate 16 of a first memory transistor 14 via a first word line (WL(2)) 28 may initially raise to approximately −0.7V for approximately 10 ns before falling to approximately −1.8V for a first read operation.

By properly biasing the memory cells 12 via the bit line (BL) 32 and the word line (WL(2)) 28, majority charge carriers 34 may be generated in the electrically floating body region 18 (e.g., first floating body (FB(1)) shown in FIG. 11A). In an exemplary embodiment, during a first read operation (Read 1), the voltage potential generated at the first floating body region 18 (FB(1)) of the first memory transistor 14 may gradually rise to approximately 0.8V.

During a first write operation, voltage potentials on the bit line (BL) 32 and the word line (WL(2)) 28 may be varied to a predetermined voltage potential to implement the first write operation. In an exemplary embodiment, an opposite data state (e.g., logic low (binary “0” data state)) detected during the first read operation (e.g., logic high (binary “1” data state)) may be written back to the first memory transistor 14. The voltage potentials on the bit line (BL) 32 may vary during a write operation. In an exemplary embodiment, a voltage potential applied to a first memory transistor 14 via a first bit line (BL) 32 may gradually fall to approximately 1.1V for approximately 20 ns before fall again to approximately 0.2V. Also, a voltage potential applied to the first word line (WL(2)) 28 may raise to approximately 0.2V from −1.8V for approximately 5 ns before falling to −0.5V for approximately 10 ns and may subsequently fall back to approximately −1.8V.

The first write operation may be accomplished via a bipolar current and majority charge carriers 34 may be depleted from the electrically floating body region 18 (e.g., FB(1)) of the memory transistor 14 of the memory cell 12 that may be juxtaposed or near the gate dielectric (which is disposed between the gate 16 and the electrically floating body region 18 (e.g., FB(1))). In an exemplary embodiment, a voltage potential at a first floating body region 18 (FB(1)) may fall to approximately 0V from 0.7V.

During a second read operation (Read 2), a data state stored in the electrically floating body region 18 (e.g., FB(0)) of the second memory transistor 14 may be read by applying a voltage potential applied to the drain region 22 of a second memory transistor 14 via the bit line (BLB) 32 may vary. In an exemplary embodiment, the voltage potential applied to the drain region 22 of the second memory transistor 14 via the bit line (BLB) 32 may fall to approximately 2.0V from 2.3V (Read 2). Also, a voltage potential applied to the second memory transistor 14 via a second word line (WL(1)) 28 may vary. In an exemplary embodiment, the voltage potential applied to the gate 16 of a first memory transistor 14 via the second word line (WL(1)) 28 may raise to approximately −0.7V from −1.8V.

By properly biasing the memory cells 12 via the bit line (BLB) 32 and the word line (WL(1)) 28, majority charge carriers 34 may be generated in the electrically floating body region 18 (e.g., second floating body (FB(0)) shown in FIG. 11A). In an exemplary embodiment, during the second read operation (Read 2), the voltage potential generated at the second floating body region 18 (FB(0)) of the second memory transistor 14 may gradually rise to approximately 0.8V.

During a second write operation, voltage potentials on the bit line (BLB) 32 and the word line (WL(1)) 28 may be varied to a predetermined voltage potential to implement the second write operation. In an exemplary embodiment, an opposite data state (e.g., logic low (binary “0” data state)) detected during the second read operation (e.g., logic high (binary “1” data state)) may be written back to the second memory transistor 14. The voltage potentials on the bit line (BLB) 32 may vary during a write operation. In an exemplary embodiment, a voltage potential applied to a second memory transistor 14 via the bit line (BLB) 32 may gradually fall to approximately 1.1V for approximately 20 ns before fall again to approximately 0.2V. Also, a voltage potential applied to the second word line (WL(1)) 28 may raise to approximately 0.2V from −1.8V for approximately 5 ns before falling to −0.5V for approximately 10 ns and may subsequently fall back to approximately −1.8V.

The second write operation may be accomplished via a bipolar current and majority charge carriers 34 may be depleted from the electrically floating body region 18 (e.g., FB(0)) of the memory transistor 14 of the memory cell 12 that may be juxtaposed or near the gate dielectric (which is disposed between the gate 16 and the electrically floating body region 18 (e.g., FB(0))). In an exemplary embodiment, a voltage potential at a second floating body region 18 (FB(0)) may fall to approximately 0V from 0.7V.

During a third read operation (Read 3), a data state stored in the electrically floating body region 18 (e.g., FB(1)) of the first memory transistor 14 may be read by applying a voltage potential applied to the drain region 22 of a first memory transistor 14 via the bit line (BL) 32. In an exemplary embodiment, the voltage potential applied to the drain region 22 of a first memory transistor 14 via the bit line (BL) 32 may rise to approximately 2.3V from 0V (Read 3) and may remain at approximately 2.3V for the third read operation. Also, a voltage potential applied to a first memory transistor 14 via a first word line (WL(2)) 28 may vary. In an exemplary embodiment, the voltage potential applied to the gate 16 of a first memory transistor 14 via a first word line (WL(2)) 28 may initially raise to approximately −0.7V for approximately 10 ns before falling to approximately −1.8V for the third read operation.

By properly biasing the memory cells 12 via the bit line (BL) 32 and the word line (WL(2)) 28, majority charge carriers 34 may be generated in the electrically floating body region 18 (e.g., first floating body (FB(1)) shown in FIG. 11A). For In an exemplary embodiment, during a third read operation (Read 3), the voltage potential generated at the first floating body region 18 (FB(1)) of the first memory transistor 14 may gradually rise to approximately 0.3V. The voltage potential generated at the first electrically floating body 18 (e.g., FB(1)) may indicate that a logic low (binary “0” data state) is stored in the first floating body region 18 (FB(1)).

During a third write operation, voltage potentials on the bit line (BL) 32 and the word line (WL(2)) 28 may be varied to a predetermined voltage potential to implement the third write operation. In an exemplary embodiment, an opposite data state (e.g., logic high (binary “1” data state)) detected during the third read operation (e.g., logic low (binary “0” data state)) may be written back to the first memory transistor 14. The voltage potentials on the bit line (BL) 32 may vary during a write operation. In an exemplary embodiment, a voltage potential applied to a first memory transistor 14 via a first bit line (BL) 32 may maintain a voltage potential of 2.3V for approximately 10 ns before fall to approximately 0V. Also, a voltage potential applied to the first word line (WL(2)) 28 may raise to approximately 0.2V from −1.8V for approximately 5 ns before falling to −0.5V for approximately 10 ns and may subsequently fall back to approximately −1.8V.

The third write operation may be accomplished via a bipolar current and majority charge carriers 34 may be accumulated in the electrically floating body region 18 (e.g., FB(1)) of the memory transistor 14 of the memory cell 12 that may be juxtaposed or near the gate dielectric (which is disposed between the gate 16 and the electrically floating body region 18 (e.g., FB(1))). In an exemplary embodiment, a voltage potential at a first floating body region 18 (FB(1)) may raise to approximately 0.7V.

During a fourth read operation (Read 4), a data state stored in the electrically floating body region 18 (e.g., FB(0)) of the second memory transistor 14 may be read by applying a voltage potential applied to the drain region 22 of the second memory transistor 14 via the bit line (BLB) 32. In an exemplary embodiment, the voltage potential applied to the drain region 22 of the second memory transistor 14 via the bit line (BLB) 32 may rise to approximately 2.3V (Read 4) and may remain at approximately 2.3V for the fourth read operation. Also, a voltage potential applied to a second memory transistor 14 via a second word line (WL(1)) 28 may vary. In an exemplary embodiment, the voltage potential applied to the gate 16 of the second memory transistor 14 via a second word line (WL(1)) 28 may initially raise to approximately −0.7V for approximately 10 ns before falling to approximately −1.8V for a fourth read operation.

By properly biasing the memory cells 12 via the bit line (BLB) 32 and the word line (WL(1)) 28, majority charge carriers 34 may be generated in the electrically floating body region 18 (e.g., first floating body (FB(0)) shown in FIG. 11A). In an exemplary embodiment, during a fourth read operation (Read 4), the voltage potential generated at the second floating body region 18 (FB(0)) of the second memory transistor 14 may gradually rise to approximately 0.3V.

During a fourth write operation, voltage potentials on the bit line (BLB) 32 and the word line (WL(1)) 28 may be varied to a predetermined voltage potential to implement the fourth write operation. In an exemplary embodiment, an opposite data state (e.g., logic high (binary “1” data state)) detected during the fourth read operation (e.g., logic low (binary “0” data state)) may be written back to the second memory transistor 14. The voltage potentials on the bit line (BLB) 32 may vary during a write operation. In an exemplary embodiment, a voltage potential applied to a second memory transistor 14 via a second bit line (BLB) 32 may fall to approximately 0V from 2.3V. Also, a voltage potential applied to the second word line (WL(1)) 28 may raise to approximately 0.2V from −1.8V for approximately 5 ns before falling to −0.5V for approximately 10 ns and may subsequently fall back to approximately −1.8V.

The fourth write operation may be accomplished via a bipolar current and majority charge carriers 34 may be accumulated in the electrically floating body region 18 (e.g., FB(0)) of the second memory transistor 14 of the memory cell 12 that may be juxtaposed or near the gate dielectric (which is disposed between the gate 16 and the electrically floating body region 18 (e.g., FB(0))). In an exemplary embodiment, a voltage potential at a second floating body region 18 (FB(0)) may raise to approximately 0.7V.

Referring to FIG. 12, there is shown a schematic block diagram of a portion of a semiconductor memory device 1200 in accordance with an alternate embodiment of the present disclosure. The semiconductor memory device 1200 may include data sense circuitry 1202 controllable and/or selectively coupled to one or more memory cell arrays 10 via one or more bit lines 32 (shown in FIG. 3). The data sense circuitry 1202 may include one or more bit line input circuitry 1204 coupled to each memory cell array 10, data sense amplifier latch circuitry 1206, data write back circuitry 1208, and/or input/output circuitry 1210.

The one or more bit line input circuitry 1204 may couple the data sense amplifier latch circuitry 1206 to one or more memory cell arrays 10. Also, the one or more bit line input circuitry 1204 may apply a hold voltage to the memory cell arrays 10 in order to hold data states (e.g., logic high (binary “1” data state) and logic low (binary “0” data state)) stored in the memory cell arrays 10.

The data sense amplifier latch circuitry 1206 may sample, sense, read, and/or determine a logic low (binary “0” data state) or a logic high (binary “1” data state) stored in one or more memory cells 12 (shown in FIG. 3) of one or more memory cell arrays 10. A reference voltage and/or current may be applied to pre-charge the data sense amplifier latch circuitry 1206 before a sample, sense, read, and/or data state determining operation. For example, during a sample, sense, read, and/or data state determining operation, the data sense amplifier latch circuitry 1206 may compare a current generated by a memory cell with an applied pre-charged reference current. In an exemplary embodiment, the pre-charged reference voltage and/or current applied to the data sense amplifier latch circuitry 1206 may have a magnitude between a magnitude of voltage/current that may represent a logic low (binary “0” data state) and a magnitude of voltage/current that may represent a logic high (binary “1” data state) stored in the memory cell 12.

The data write back circuitry 1208 may modify and/or write back a data state determined by the data sense amplifier latch circuitry 1206. In an exemplary embodiment, the data write back circuitry 1208 may restore and/or refresh data states for the plurality of memory cells 12 of the memory cell array 10.

The input/output circuitry 1210 may allow external access to the plurality of memory cells 12 in the plurality of memory cell arrays 10 via the data sense amplifier latch circuitry 1206. The input/output circuitry 1208 may selectively and/or controllably output a data state stored in the memory cells 12 of the memory cell arrays 10. In an exemplary embodiment, the input/output circuitry 1208 may include pass gates and/or column switch circuitry to facilitate and/or implement various operations on the memory cells 12 of the memory cell arrays 10.

The memory cell selection and control circuitry 38 may control one or more selected memory cells 12 of the memory cell arrays 10 coupled to the data sense circuitry 1202. In an exemplary embodiment, the memory cell selection and control circuitry 38 may include a plurality of word lines (WL) 28, a plurality of source lines (SL) 30, word line (WL) decoders and/or drivers, and/or source line (SL) decoders and/or drivers. The memory cell selection and control circuitry 38 may apply one or more control signals via the plurality of word lines (WL) 28 and/or the plurality of source lines (SL) 30. Also, the memory cell selection and control circuitry 38 may include pass gates and/or row switch circuitry (not shown) to selectively activate the memory cells 12 in order to perform various operations.

Referring to FIG. 13, there is shown a schematic diagram of data sense circuitry 1302 in accordance with an embodiment of the present disclosure. The data sense circuitry 1302 may include one or more bit line input circuitry 1304 and 1306 coupled to one or more memory cells 12 (not shown), data sense amplifier latch circuitry 1308, input/output circuitry 1310, pre-charge circuitry 1312, and/or writeback circuitry 1314 and 1316.

Each bit line input circuitry 1304 and 1306 may include a switching transistor coupling the data sense amplifier latch circuitry 1308 to the one or more memory cells 12 (not shown). In an exemplary embodiment, the bit line input circuitry 1304 may be coupled to a memory cell 12 (not shown) via bit line (BL) 32 (e.g., BLL<1>). Also, the bit line input circuitry 1306 may be coupled to a memory cell 12 (not shown) via bit line (BL) 32 (e.g., BLR<1>).

The pre-charge circuitry 1312 may include one or more transistors 1324 and 1326 for setting and/or charging the data sense amplifier latch circuitry 1308 to a reference voltage and/or current before a sample, sense, read, and/or data state determining operation. In an exemplary embodiment, the transistors 1324 and 1326 of the pre-charge circuitry 1312 are biased via different voltage and/or current signals. For example, the transistor 1324 may be biased via inputs VBLPRE_SENREF and/or BLPRE_REFSEN, and the transistor 1326 may be biased via inputs VBLPRE and/or BLPRE.

During operation, the transistors 1324 and 1326 of the pre-charge circuitry 1312 may be biased to “clear” or “reset” the data sense amplifier latch circuitry 1308. In an exemplary embodiment, the data sense amplifier latch circuitry 1308 may have a “history” (residual charges in the data sense amplifier latch circuitry 1308 from previous operations) and the transistors 1324 and 1326 may be biased to “clear” the “history” of the data sense amplifier latch circuitry 1308. After “clearing” or “resetting” the data sense amplifier latch circuitry 1308, the transistor 1324 may be biased in order to provide a reference voltage and/or current to the data sense amplifier latch circuitry 1308.

The data sense amplifier latch circuitry 1308 may include a sense node (SN) coupled to a bit line 32 (e.g., BLL<1> and/or BLR<1>) and a reference node (RN) coupled to the transistor 1324 of the pre-charge circuitry 1312. The sense node (SN) may be set to and/or maintained at a voltage and/or current provided by a memory cell 12 (not shown), while the reference node (RN) may be set to and/or maintained at a reference voltage and/or current provided by the pre-charge circuitry 1312. In an exemplary embodiment, the bit line input circuitry 1306 may turn off and block voltage and/or current from a memory cell 12 (not shown) via a bit line 32 (e.g., BLR<1>). Meanwhile, the bit line input circuitry 1304 may turn on and the sense node (SN) may receive voltage and/or current from a memory cell 12 (not shown) via a bit line 32 (e.g., BLL<1>). In another embodiment, the bit line input circuitry 1304 may turn off and block voltage and/or current from a memory cell 12 (not shown) via a bit line (e.g., BLL<1>). Meanwhile, the bit line input circuitry 1306 may turn on and the sense node (SN) may receive voltage and/or current from a memory cell 12 (not shown) via a bit line 32 (e.g., BLR<1>). The data sense amplifier latch circuitry 1308 may determine a data state based on the voltage and/or current at the sense node (SN) and the voltage and/or current at the reference node (RN).

The voltage and/or current provided by a memory cell 12 at the sense node (SN) and the reference voltage and/or current provided by the pre-charge circuitry 1312 at the reference node (RN) may produce a voltage and/or current differential between the sense node (SN) and the reference node (RN). The data sense amplifier latch circuitry 1308 may include a plurality of transistors 1328-1334 arranged in a cross-coupled configuration that may amplify the voltage and/or current difference between the sense node (SN) and the reference node (RN) in order to determine a data state stored in a memory cell 12 (not shown).

In an exemplary embodiment, in the event that a logic high (binary “1” data state) is stored in a memory cell 12, the voltage and/or current provided by the memory cell 12 at the sense node (SN) may be higher than the reference voltage and/or current provided by the pre-charge circuitry 1312 at the reference node (RN). The voltage and/or current provided by the memory cell 12 may be received at the sense node (SN) and may turn on transistor 1332 to “pull” the reference node (RN) low and may turn off transistor 1334 and may turn on transistor 1330. The sense node (SN) may be “pulled” to a voltage potential (e.g., VDD1 voltage potential) when transistor 1336 is turned on via signal line (PSAEN). In other exemplary embodiments, the transistor 1330 may not turn on until the transistor 1336 is turned on. The signal applied via the signal line (PSAEN) may be pulsed low before the sense node (SN) is switched above a threshold voltage level. In an exemplary embodiment, the voltage potential (VDD1) may be supplied by an independently variable voltage source in order to perform a read operation and/or a write operation. Also, a voltage potential (NSRC_SA) applied to the data sense amplifier latch circuitry 1308 may be coupled via a variable voltage source to an appropriate voltage to perform one or more operations.

In another exemplary embodiment, in the event that a logic low (binary “0” data state) is stored in a memory cell 12, the voltage and/or current provided by the memory cell 12 at the sense node (SN) may be lower than the reference voltage and/or current provided by the pre-charge circuitry 1312 at the reference node (RN). The reference voltage and/or current provided by the pre-charge circuitry 1312 at the reference node (RN) may turn on transistor 1334 to “pull” the sense node (SN) low and may turn off transistor 1332 and may turn on transistor 1328. In an exemplary embodiment, transistor 1328 may not turn on until transistor 1336 is turned on. The reference node (RN) may be “pulled” to a voltage potential (e.g., VDD1 voltage potential) via a signal line (VDD1). The signal applied via the signal line (PSAEN) may be pulsed low before the reference node (RN) is switched above a threshold voltage level.

The data sense amplifier latch circuitry 1308 may sense, sample, and/or determine the data state of a memory cell 12 (not shown), and store the data state in the data sense amplifier latch circuitry 1308. The data state stored in the data sense amplifier latch circuitry 1308 may be read and/or accessed via transistors 1338 and 1340 of the input/output circuitry 1310.

The data state stored in the data sense amplifier latch circuitry 1308 may be written back to a memory cell 12 (not shown) via the writeback circuitry 1314 and/or 1316. In an exemplary embodiment, the data sense amplifier latch circuitry 1308 may output via the reference node (RN) an opposite data state of the data state stored at the sense node (SN) of the data sense amplifier latch circuitry 1308. For example, if a logic low (binary “0” data state) is detected at the sense node (SN) of the data sense amplifier latch circuitry 1308, the data sense amplifier latch circuitry 1308 may output an opposite data state (logic high (binary “1” data state)) via the reference node (RN). In particular, a logic low (binary “0” data state) may be inputted via the one or more bit line input circuitries 1304 and 1306 and/or the input/output circuitry 1310 to the sense node (SN) of the data sense amplifier latch circuitry 1308. The logic low (binary “0” data state) may be detected at the sense node (SN) of the data sense amplifier latch circuitry 1308 and stored. The data sense amplifier latch circuitry 1308 may store and/or output an opposite data state (logic high (binary “1” data state)) at the reference node (RN). The output opposite data state may be written back to a memory cell 12 (not shown) via the writeback circuitry 1314 and/or 1316 and/or input/output circuitry 1310.

Referring to FIG. 14, there is shown a schematic diagram of data sense circuitry 1402 in accordance with an alternate embodiment of the present disclosure. The data sense circuitry 1402 may include one or more bit line input circuitry 1404 and 1406 coupled to one or more memory cells 12 (not shown), data sense amplifier latch circuitry 1408, input/output circuitry 1410, pre-charge circuitry 1412, and/or writeback circuitry 1414 and 1416. The data sense circuitry 1402 has a similar schematic configuration and/or components as the data sense circuitry 1302, except that the memory cells 12 (not shown) are coupled to the data sense amplifier circuitry 1408 via different bit lines 32 (e.g., BLL<1> and BLR<1>).

Each bit line input circuitry 1404 and 1406 may include a switching transistor coupling the data sense amplifier latch circuitry 1408 to the one or more memory cells 12 (not shown). In an exemplary embodiment, the bit line input circuitry 1404 may be coupled to a memory cell 12 (not shown) via bit line (BL) (e.g., BLL<1>). Also, the bit line input circuitry 1406 may be coupled to a memory cell 12 (not shown) via a disparate bit line (BL) 32 (e.g., BLR<1>).

The pre-charge circuitry 1412 may include one or more transistors 1424 and 1426 for setting and/or charging the data sense amplifier latch circuitry 1408 to a reference voltage and/or current before a sample, sense, read, and/or data state determining operation. In an exemplary embodiment, the transistors 1424 and 1426 of the pre-charge circuitry 1412 are biased via different voltage and/or current signals. For example, the transistor 1424 may be biased via inputs VBLPRE_SENREF and/or BLPRE_REFSEN, and the transistor 1426 may be biased via inputs VBLPRE and/or BLPRE.

During operation, the transistors 1424 and 1426 of the pre-charge circuitry 1412 may be biased to “clear” or “reset” the data sense amplifier latch circuitry 1408. In an exemplary embodiment, the data sense amplifier latch circuitry 1408 may have a “history” (or residual charges within the data sense amplifier latch circuitry 1408 from previous operations) and the transistors 1424 and 1426 may be biased to “clear” the “history” of the data sense amplifier latch circuitry 1408. After “clearing” or “resetting” the data sense amplifier latch circuitry 1408, the transistor 1424 and/or 1426, may be biased in order to provide a reference voltage and/or current to the data sense amplifier latch circuitry 1408. For example, in the event that the data sense amplifier latch circuitry 1408 receives voltage and/or current from the memory cell 12 (not shown) via bit line 32 (e.g., BLL<1>), the transistor 1424 may be biased in order to provide a reference voltage and/or current to the data sense amplifier latch circuitry 1408. Also, in the event that the data sense amplifier latch circuitry 1408 receives voltage and/or current from the memory cell 12 (not shown) via bit line 32 (e.g., BLR<1>), the transistor 1426 may be biased in order to provide a reference voltage and/or current to the data sense amplifier latch circuitry 1408.

The data sense amplifier latch circuitry 1408 may include a sense node (SN) coupled to a bit line 32 (e.g., BLL<1>) and a reference node (RN) coupled to a bit line 32 (e.g., BLR<1>). The sense node (SN) may be set to and/or maintained at a voltage and/or current provided by a memory cell 12 (not shown), while the reference node (RN) may be set to and/or maintained at a reference voltage and/or current provided by the pre-charge circuitry 1412, and vice-versa. In an exemplary embodiment, the bit line input circuitry 1406 may turn off and block voltage and/or current from a memory cell 12 (not shown) via a bit line 32 (e.g., BLR<1>). Meanwhile, the bit line input circuitry 1404 may turn on and the sense node (SN) may receive voltage and/or current from a memory cell 12 (not shown) via a bit line 32 (e.g., BLL<1>). In another embodiment, the bit line input circuitry 1404 may turn off and block voltage and/or current from a memory cell 12 (not shown) via a bit line 32 (e.g., BLL<1>). Meanwhile, the bit line input circuitry 1406 may turn on and the reference node (RN) may receive voltage and/or current from a memory cell 12 (not shown) via a bit line 32 (e.g., BLR<1>). The data sense amplifier latch circuitry 1408 may determine a data state based on the voltage and/or current at the sense node (SN) and the voltage and/or current at the reference node (RN).

The voltage and/or current at the sense node (SN) and the voltage and/or current at the reference node (RN) may produce a voltage and/or current differential between the sense node (SN) and the reference node (RN) of the data sense amplifier latch circuitry 1408. The data sense amplifier latch circuitry 1408 may include a plurality of transistors 1428-1434 arranged in a cross-coupled configuration that may amplify the voltage and/or current difference between the sense node (SN) and the reference node (RN) in order to determine a data state stored in a memory cell 12 (not shown).

In an exemplary embodiment, in the event that a logic high (binary “1” data state) is stored in a memory cell 12, the voltage and/or current provided by the memory cell 12 at the sense node (SN) may be higher than the reference voltage and/or current provided by the pre-charge circuitry 1412 at the reference node (RN). The voltage and/or current provided by the memory cell 12 may be received at the sense node (SN) and may turn on transistor 1432 to “pull” the reference node (RN) low and may turn off transistor 1434 and may turn on transistor 1430. The sense node (SN) may be “pulled” to a voltage potential (e.g., VDD1 voltage potential) when transistor 1436 is turned on via signal line (PSAEN). In other exemplary embodiments, the transistor 1430 may not turn on until the transistor 1436 is turned on. The signal applied via the signal line (PSAEN) may be pulsed low before the sense node (SN) is switched above a threshold voltage level. In an exemplary embodiment, the voltage potential (VDD1) may be supplied by an independently variable voltage source in order to perform a read operation and/or a write operation. Also, a voltage potential (NSRC_SA) applied to the data sense amplifier latch circuitry 1408 may be coupled via a variable voltage source to an appropriate voltage to perform one or more operations.

In another exemplary embodiment, in the event that a logic low (binary “0” data state) is stored in a memory cell 12, the voltage and/or current provided by the memory cell 12 at the sense node (SN) may be lower than the reference voltage and/or current provided by the pre-charge circuitry 1412 at the reference node (RN). The reference voltage and/or current provided by the pre-charge circuitry 1412 at the reference node (RN) may turn on transistor 1434 to “pull” the sense node (SN) low and may turn off transistor 1432 and may turn on transistor 1428. In an exemplary embodiment, transistor 1428 may not turn on until transistor 1436 is turned on. The reference node (RN) may be “pulled” to a voltage potential (e.g., VDD1 voltage potential) via a signal line (VDD1). The signal applied via the signal line (PSAEN) may be pulsed low before the reference node (RN) is switched above a threshold voltage level. Also, the reference node (RN) of the data sense amplifier latch circuitry 1408 may sense, sample, and/or determine the data state of a memory cell 12 (not shown) and output the detected data state (or opposite of the detected data state) via the sense node (SN).

The data sense amplifier latch circuitry 1408 may sense, sample, and/or determine the data state of a memory cell 12 (not shown), and store the data state in the data sense amplifier latch circuitry 1408. The data state stored in the data sense amplifier latch circuitry 1408 may be read and/or accessed via transistors 1438 and 1440 of the input/output circuitry 1410.

The data state stored in the data sense amplifier latch circuitry 1408 may be written back to a memory cell 12 (not shown) via the writeback circuitry 1414 and/or 1416. In an exemplary embodiment, the data sense amplifier latch circuitry 1408 may output via the reference node (RN) an opposite data state of the data state stored at the sense node (SN) of the data sense amplifier latch circuitry 1408. For example, if a logic low (binary “0” data state) is detected at the sense node (SN) of the data sense amplifier latch circuitry 1408, the data sense amplifier latch circuitry 1408 may output an opposite data state (logic high (binary “1” data state)) via the reference node (RN). In particular, a logic low (binary “0” data state) may be inputted via the one or more bit line input circuitries 1404 and 1406 and/or the input/output circuitry 1410 to the sense node (SN) of the data sense amplifier latch circuitry 1408. The logic low (binary “0” data state) may be detected at the sense node (SN) of the data sense amplifier latch circuitry 1408 and stored. The data sense amplifier latch circuitry 1408 may store and/or output an opposite data state (logic high (binary “1” data state)) at the reference node (RN). The output opposite data state may be written back to a memory cell 12 (not shown) via the writeback circuitry 1414 and/or 1416 and/or input/output circuitry 1410.

Referring to FIG. 15, there is shown a schematic diagram of data sense circuitry 1502 in accordance with an alternate embodiment of the present disclosure. The data sense circuitry 1502 may include one or more bit line input circuitry 1504 and 1506 coupled to one or more memory cells 12 (not shown), data sense amplifier latch circuitry 1508, input/output circuitry 1510, and/or pre-charge circuitry 1512. The data sense circuitry 1502 has a similar schematic configuration and/or components as the data sense circuitry 1402, except that the data sense circuitry 1502 does not have writeback circuitry.

Each bit line input circuitry 1504 and 1506 may include a switching transistor coupling the data sense amplifier latch circuitry 1508 to the one or more memory cells 12 (not shown). In an exemplary embodiment, the bit line input circuitry 1504 may be coupled to a memory cell 12 (not shown) via bit line (BL) (e.g., BLL<1>). Also, the bit line input circuitry 1506 may be coupled to a memory cell 12 (not shown) via a disparate bit line (BL) 32 (e.g., BLR<1>).

The pre-charge circuitry 1512 may include one or more transistors 1524 and 1526 for setting and/or charging the data sense amplifier latch circuitry 1508 to a reference voltage and/or current before a sample, sense, read, and/or data state determining operation. In an exemplary embodiment, the transistors 1524 and 1526 of the pre-charge circuitry 1512 are biased via different voltage and/or current signals. For example, the transistor 1524 may be biased via inputs VBLPRE_SENREF, and/or BLPRE_REFSEN and the transistor 1526 may be biased via inputs VBLPRE and/or BLPRE.

During operation, the transistors 1524 and 1526 of the pre-charge circuitry 1512 may be biased to “clear” or “reset” the data sense amplifier latch circuitry 1508. In an exemplary embodiment, the data sense amplifier latch circuitry 1508 may have a “history” (or residual charges within the data sense amplifier latch circuitry 1508 from previous operations) and the transistors 1524 and 1526 may be biased to “clear” the “history” of the data sense amplifier latch circuitry 1508. After “clearing” or “resetting” the data sense amplifier latch circuitry 1508, the transistor 1524 and/or 1526, may be biased in order to provide a reference voltage and/or current to the data sense amplifier latch circuitry 1508. For example, in the event that the data sense amplifier latch circuitry 1508 receives voltage and/or current from the memory cell 12 (not shown) via bit line 32 (e.g., BLL<1>), the transistor 1524 may be biased in order to provide a reference voltage and/or current to the data sense amplifier latch circuitry 1508. Also, in the event that the data sense amplifier latch circuitry 1508 receives voltage and/or current from the memory cell 12 (not shown) via bit line 32 (e.g., BLR<1>), the transistor 1526 may be biased in order to provide a reference voltage and/or current to the data sense amplifier latch circuitry 1508.

The data sense amplifier latch circuitry 1508 may include a sense node (SN) coupled to a bit line 32 (e.g., BLL<1>) and a reference node (RN) coupled to a bit line 32 (e.g., BLR<1>). The sense node (SN) may be set to and/or maintained at a voltage and/or current provided by a memory cell 12 (not shown), while the reference node (RN) may be set to and/or maintained at a reference voltage and/or current provided by the pre-charge circuitry 1512, and vice-versa. In an exemplary embodiment, the bit line input circuitry 1506 may turn off and block voltage and/or current from a memory cell 12 (not shown) via a bit line (e.g., BLR<1<). Meanwhile, the bit line input circuitry 1504 may turn on and the sense node (SN) may receive voltage and/or current from a memory cell 12 (not shown) via a bit line 32 (e.g., BLL<1>). In another embodiment, the bit line input circuitry 1504 may turn off and block voltage and/or current from a memory cell 12 (not shown) via a bit line 32 (e.g., BLL<1>). Meanwhile, the bit line input circuitry 1506 may turn on and the reference node (RN) may receive voltage and/or current from a memory cell 12 (not shown) via a bit line 32 (e.g., BLR<1>). The data sense amplifier latch circuitry 1508 may determine a data state based on the voltage and/or current at the sense node (SN) and the voltage and/or current at the reference node (RN).

The voltage and/or current at the sense node (SN) and the voltage and/or current at the reference node (RN) may produce a voltage and/or current differential between the sense node (SN) and the reference node (RN) of the data sense amplifier latch circuitry 1508. The data sense amplifier latch circuitry 1508 may include a plurality of transistors 1528-1534 arranged in a cross-coupled configuration that may amplify the voltage and/or current difference between the sense node (SN) and the reference node (RN) in order to determine a data state stored in a memory cell 12 (not shown).

In an exemplary embodiment, in the event that a logic high (binary “1” data state) is stored in a memory cell 12, the voltage and/or current provided by the memory cell 12 at the sense node (SN) may be higher than the reference voltage and/or current provided by the pre-charge circuitry 1512 at the reference node (RN). The voltage and/or current provided by the memory cell 12 may be received at the sense node (SN) and may turn on transistor 1532 to “pull” the reference node (RN) low and may turn off transistor 1534 and may turn on transistor 1530. The sense node (SN) may be “pulled” to a voltage potential (e.g., VDD1 voltage potential) when transistor 1536 is turned on via signal line (PSAEN). In other exemplary embodiments, the transistor 1530 may not turn on until the transistor 1536 is turned on. The signal applied via the signal line (PSAEN) may be pulsed low before the sense node (SN) is switched above a threshold voltage level. In an exemplary embodiment, the voltage potential (VDD1) may be supplied by an independently variable voltage source in order to perform a read operation and/or a write operation. Also, a voltage potential (NSRC_SA) applied to the data sense amplifier latch circuitry 1508 may be coupled via a variable voltage source to an appropriate voltage to perform one or more operations.

In another exemplary embodiment, in the event that a logic low (binary “0” data state) is stored in a memory cell 12, the voltage and/or current provided by the memory cell 12 at the sense node (SN) may be lower than the reference voltage and/or current provided by the pre-charge circuitry 1512 at the reference node (RN). The reference voltage and/or current provided by the pre-charge circuitry 1512 at the reference node (RN) may turn on transistor 1534 to “pull” the sense node (SN) low and may turn off transistor 1532 and may turn on transistor 1528. In an exemplary embodiment, transistor 1528 may not turn on until transistor 1536 is turned on. The reference node (RN) may be “pulled” to a voltage potential (e.g., VDD1 voltage potential) via a signal line (VDD1). The signal applied via the signal line (PSAEN) may be pulsed low before the reference node (RN) is switched above a threshold voltage level. Also, the reference node (RN) of the data sense amplifier latch circuitry 1408 may sense, sample, and/or determine the data state of a memory cell 12 (not shown) and output the detected data state (or opposite of the detected data state) via the sense node (SN).

The data sense amplifier latch circuitry 1508 may sense, sample, and/or determine the data state of a memory cell 12 (not shown), and store the data state in the data sense amplifier latch circuitry 1508. The data state stored in the data sense amplifier latch circuitry 1508 may be read and/or accessed via transistors 1538 and 1540 of the input/output circuitry 1510. Also, the data sense amplifier latch circuitry 1508 may writeback a data state detected. In an exemplary embodiment, the data sense amplifier latch circuitry 1508 may detect a data state of a memory cell 12 (not shown) at the sense node (SN) coupled to the one or more bit line input circuitry 1504 and/or 1506 and stored. Thereafter, the data sense amplifier latch circuitry 1508 may output the data state detected via the sense node (SN) and written back to the memory cell 12 (not shown) via the one or more bit line input circuitry 1504 and 1506.

Referring to FIGS. 16A, 16B, 16C, and 16D there are shown control signal voltage waveforms for various operations in accordance with an embodiment of the present disclosure. The control signal voltage waveforms may be described with reference to the components of the data sense circuitry 1302 as illustrated in FIG. 13. However, it should be appreciated that the control signals voltage waveforms illustrated in FIGS. 16A, 16B, 16C, and 16D may be implemented by the data sense circuitry 1302 illustrated in FIG. 13, the data sense circuitry 1402 illustrated in FIG. 14 and/or the data sense circuitry 1502 illustrated in FIG. 15. For example, one or more data states from data buses (e.g., DB<0,1> and/or nDB<0,1>) may be written to the sense node (SN) and/or the reference node (RN) of a data sense amplifier latch circuitry 1308. The input/output circuitry 1310 may couple the data sense amplifier latch circuitry 1308 to the data buses (e.g., DB<0,1> and/or nDB<0,1>). A voltage potential (YDB) may be applied to the gate of the transistors 1338 and 1340 of the input/output circuitry 1310 to couple the one or more data states on the data buses (e.g., DB<0,1> and/or nDB<0,1>) to the data sense amplifier latch circuitry 1308. In an exemplary embodiment, a logic high (binary “1” data state) may be written to the data sense amplifier latch circuitry 1308 (shown in FIG. 16B). For example, the voltage potential (YDB) applied to the input/output circuitry 1310 may raise to approximately 1.4V from 0V to bias the transistors 1338 and 1340 for coupling the one or more data buses (e.g., DB<0,1> and/or nDB<0,1>) to the data sense amplifier latch circuitry 1308. The sense node (SN) of the data sense amplifier latch circuitry 1308 may receive the data states (e.g., logic high (binary “1” data state)) on the data buses (e.g., DB<0,1> and/or nDB<0,1>). The voltage potential at sense node (SN) of the data sense amplifier latch circuitry 1308 may raise to approximately 1.4V from 0V. The reference node (RN) of the data sense amplifier latch circuitry 1308 may receive a voltage potential opposite/complement of a data state stored in the memory cell 12. For example, when a logic low (binary “0” data state) is stored in the memory cell 12, the reference node (RN) may receive a voltage potential of a logic high (binary “1” data state).

In another exemplary embodiment, a logic low (binary “0” data state) may be written to the data sense amplifier latch circuitry 1308 (as shown in FIG. 16C). As discussed above, the voltage potential (YDB) applied to the input/output circuitry 1310 may raise to approximately 1.4V from 0V for coupling the one or more data buses (e.g., DB<0,1> and/or nDB<0,1> to the data sense amplifier latch circuitry 1308. The sense node (SN) of the data sense amplifier latch circuitry 1308 may receive the data states (e.g., logic low (binary “0” data state)) on the data buses (e.g., DB<0,1> and/or nDB<0,1>). The reference node (RN) data sense amplifier latch circuitry 1308 may receive the opposite/complement data state (e.g., logic high (binary “1” data state)) on the data buses (e.g., DB<0,1> and/or nDB<0,1>). The voltage potential at reference node (RN) of the data sense amplifier latch circuitry 1308 may raise to approximately 1.2V from 0V.

The one or more data states received at the sense node (SN) and/or the reference node (RN) of the data sense amplifier latch circuitry 1308 may be written to one or more memory cells 12. The one or more writeback circuitries 1314 and 1316 may write the one or more data states received at the data sense amplifier latch circuitry 1308 to the one or more memory cells 12. For example, a voltage potential (EQ_WBL) may be applied to the gate 16 of the writeback circuitry 1316. In an exemplary embodiment, the voltage potential (EQ_WBL) may raise to approximately 1.4V from 0V to write the one or more data states from the data sense amplifier latch circuitry 1308 to the memory cell 12. In an exemplary embodiment, when writing a logic low (binary “0” data state), the voltage potential at the sense node (SN) at the data sense amplifier latch circuitry 1308 may be maintained approximately at 0V. The voltage potential at the reference node (RN) may be written to the bit line (BL) 32 (BLL<1>) (as shown in FIG. 16C). As shown in FIG. 16C, the voltage potential on the bit line (BL) 32 (BLL<1>) may gradually raise to approximately 1V. In another exemplary embodiment, when writing a logic high (binary “1” data state), the voltage potential at the sense node (SN) may be maintained approximately at 1.4V and the voltage potential at the reference node (RN) at the data sense amplifier latch circuitry 1308 may be maintained at approximately 0V. The voltage potential at the reference node (RN) of the data sense amplifier latch circuitry 1308 may be written to the bit line (BL) 32 (BLL<1>). As shown in FIG. 16B, the voltage potential on the bit line (BL) 32 (BLL<0>) may be raised to approximately 0.3V and a logic high (binary “1” data state) may be written to the memory cell 12.

The bit line (BL) 32 (e.g., BLL<1> and/or BLR<1>) and the data sense amplifier latch circuitry 1308 may be precharged to perform a read operation. The pre-charge circuitry 1312 may precharge the bit line (BL) 32 (e.g., BLL<1> and/or BLR<1>) and/or the data sense amplifier latch circuitry 1308. The transistors 1324 and 1326 of the pre-charge circuitry 1312 may be independently controlled. For example, the transistor 1324 of the pre-charge circuitry 1312 may be independently controlled by a voltage potential (VBLPRE_SENREF) applied to the source region 20 of the transistor 1324 and a voltage potential (BLPRE_REFSEN) applied to the gate 16 of the transistor 1324. Also, the transistor 1326 of the pre-charge circuitry 1312 may be independently controlled by a voltage potential (VBLPRE) applied to the source region 20 of the transistor 1326 and a voltage potential (BLPRE) applied to the gate 16 of the transistor 1326. In an exemplary embodiment, the voltage potential (VBLPRE_SENREF) applied to the source region 20 of the transistor 1324 may remain constant at 0V and the voltage potential (BLPRE_REFSEN) applied to the gate 16 of the transistor 1324 may raise to approximately 1.4V from 0V. Also, the voltage potential (VBLPRE) applied to the source region 20 of the transistor 1326 may remain constant at 0V and a voltage potential (BLPRE) applied to the gate 16 of the transistor 1326 may raise to approximately 1.4V from 0V.

For example, the voltage potential (BLPRE) may be external to the data sense amplifier latch circuitry 1308 wherein the voltage potential (BLPRE) may be isolated from the data sense amplifier latch circuitry 1308 by the one or more bit line input circuitries 1304 and 1306. The external voltage potential (BLPRE) may precharge bit lines (BL) 32 coupled to one or more memory cells 12. Also, the voltage potential (BLPRE) may be internal to the data sense amplifier latch circuitry 1308 wherein the voltage potential (BLPRE) may not be isolated from the data sense amplifier latch circuitry 1308 by the one or more bit line input circuitries 1304 and 1306. The internal voltage potential (BLPRE) may precharge the data sense amplifier latch circuitry 1308 and/or set a reference voltage/current for the data sense amplifier latch circuitry 1308. For example, the internal voltage potential (BLPRE) may set the voltage potential at sense node (SN) and/or the reference node (RN) of the data sense amplifier latch circuitry 1308 to 0V.

A voltage potential (PSAEN) may be applied to the data sense amplifier latch circuitry 1308 via the transistor 1336. The voltage potential (PSAEN) may bias the data amplifier latch circuitry 1308 to perform various functions. For example, the voltage potential (PSAEN) may precharge the data sense amplifier latch circuitry 1308 by raise to approximately 1.6V from 0V.

After precharging the data sense amplifier latch circuitry 1308, the data sense amplifier latch circuitry 1308 may begin read one or more data states from the memory cell 12. A voltage potential (ISOL_RD) may be applied to the bit line input circuitry 1304 in order to couple the data sense amplifier latch circuitry 1308 to the memory cells 12. In an exemplary embodiment, the voltage potential (ISOL_RD) may raise to approximately 1.4V from 0V to couple the data sense amplifier latch circuitry 1308 to the one or more memory cells 12. During the read operation, the voltage potential (PSAEN) applied to the data sense amplifier latch circuitry 1308 may be varied. In an exemplary embodiment, the voltage potential (PSAEN) applied to the data sense amplifier latch circuitry 1308 may fall to approximately 0V from 1.6V. In an exemplary embodiment, when a logic high (binary “1” data state) is stored in a memory cell 12, the voltage potential at the sense node (SN) of the data sense amplifier latch circuitry 1308 may raise from 0V to approximately 1.4V, while the voltage potential at the reference node (RN) may be maintained at approximately 0V and a logic high (binary “1” data state) may be written to the memory cell 12 (see FIG. 16B). Also, the voltage potential on the bit line (BL) 32 (BLL<1>) may remain at approximately 0V. In another exemplary embodiment, when a logic low (binary “0” data state) is stored in a memory cell 12, the voltage potential at the reference node (RN) of the data sense amplifier latch circuitry 1308 may raise from 0V to approximately 1.4V, while the voltage potential at the sense node (SN) may be maintained at approximately 0V. Also, the voltage potential on the bit line (BL) 32 (BLL<0>) may increase to approximately 0.8V. The voltage potential (VBLPRE_SENREF) may be applied to the reference node (RN) of the data sense amplifier latch circuitry 1308 via the transistor 1524 of the pre-charge circuitry 1512 to set a reference voltage potential. For example, the voltage potential (VBLPRE_SENREF) applied to the reference node (RN) of the data sense amplifier latch circuitry 1308 may be 100 mV.

The one or more data states stored in the memory cells 12 may be detected by the data sense amplifier latch circuitry 1308, a writeback operation may be performed to write the detected data states or an opposite of the detected data state back to the memory cells 12. For example, the voltage potential (EQ_WBL) may be applied to the writeback circuitry 1316 to write the detected data states back to the memory cells 12. In an exemplary embodiment, the voltage potential (EQ_WBL) may raise to approximately 1.4V from 0V to enable the writeback circuitry 1316 to perform the writeback operation. The writeback circuitry 1316 may write a detected data state or an inverted detected data state back to the memory cell 12 via bit line (BL) 32. In an exemplary embodiment, when writing a logic high (binary “1” data state) back to a memory cell 12 (e.g., invert of detected logic high (binary “1” data state)), the voltage potential on the bit line (BL) 32 (e.g., BLL<0>) may remain at approximately between 0V to 0.4V. In another exemplary embodiment, when writing a logic low (binary “0” data state) back to a memory cell 12 (e.g., invert of detected logic low (binary “0” data state)), the voltage potential on the bit line (BL) 32 (e.g., BLL<1>) may gradually raise to approximately 0.8V to 1V to write the data state back to the memory cell 12.

The data sense amplifier latch circuitry 1308 may be precharged for the second time in order to perform a read operation. The data sense amplifier latch circuitry 1308 may be precharged in a similar manner (e.g., similar voltage potentials) as discussed above. Also, the data sense amplifier latch circuitry 1308 may detect one or more data states of the memory cells 12 in a similar manner as discussed above, however a write back operation does not have to be performed after the read operation.

At this point it should be noted that reading from and/or writing to a semiconductor memory device in accordance with the present disclosure as described above typically involves the generation of control signals to some extent. This control signal generation may be implemented in hardware or software. For example, specific electronic components may be employed in a semiconductor memory device or similar or related circuitry for implementing the functions associated with reading from and/or writing to the semiconductor memory device in accordance with the present disclosure as described above. Alternatively, one or more processors operating in accordance with instructions may implement the functions associated with reading from and/or writing to a semiconductor memory device in accordance with the present disclosure as described above. If such is the case, it is within the scope of the present disclosure that such instructions may be stored on one or more processor readable storage media (e.g., a magnetic disk or other storage medium), or transmitted to one or more processors via one or more signals embodied in one or more carrier waves.

The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein. 

1. An apparatus comprising: a first memory cell array comprising a first plurality of memory cells arranged in a matrix of rows and columns; a second memory cell array comprising a second plurality of memory cells arranged in a matrix of row and columns; a data sense amplifier latch circuitry comprising a first input node and a second input node; a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry; a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry; a precharge circuitry coupled to the first input node and the second input node for precharging the first input node and the second input node to a first pre-charged voltage level and a second pre-charged voltage level; and a keeper circuitry coupled to the first bit line input circuitry and the second bit line input circuitry for maintaining the first pre-charged voltage level at the first input node and the second pre-charged voltage level at the second input node, respectively.
 2. The apparatus according to claim 1, wherein the data sense amplifier latch circuitry further comprises a plurality of transistors arranged in a cross-coupled configuration that are configured to amplify a voltage or current difference between the first input node and the second input node.
 3. The apparatus according to claim 1, wherein the first bit line input circuitry is configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry via a first bit line.
 4. The apparatus according to claim 3, wherein the second bit line input circuitry is configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry via a second bit line.
 5. The apparatus according to claim 1, wherein the first bit line input circuitry comprises a switch circuitry configured to couple the data sense amplifier latch circuitry to the first memory cell array and a hold circuitry coupled to the first memory cell array to maintain one or more data states stored in the first memory cell array.
 6. The apparatus according to claim 5, wherein the second bit line input circuitry comprises a switch circuitry configured to couple the data sense amplifier latch circuitry to the second memory cell array and a hold circuitry coupled to the second memory cell array to maintain one or more data states stored in the second memory cell array.
 7. The apparatus according to claim 1, wherein the pre-charge circuitry has a first transistor configured to pre-charge the first input node of the data sense amplifier latch circuitry and a second transistor configured to pre-charge the second input node of the data sense amplifier latch circuitry.
 8. The apparatus according to claim 1, further comprising an input/output circuitry coupled to the data sense amplifier latch circuitry configured to output one or more data states of at least one of the first memory cell array and the second memory cell array detected by the data sense amplifier latch circuitry.
 9. The apparatus according to claim 8, wherein the input/output circuitry comprises a first transistor coupled to the first input node of the data sense amplifier latch circuitry and a second transistor coupled to the second input node of the data sense amplifier latch circuitry.
 10. The apparatus according to claim 1, wherein the keeper circuitry comprises a first transistor coupled to the first bit line input circuitry and the first memory cell array and a second transistor coupled to the second bit line input circuitry and the second memory cell array.
 11. The apparatus according to claim 1, further comprising a first writeback circuitry coupled to the first memory cell array and the data sense amplifier latch circuitry.
 12. The apparatus according to claim 11, further comprising a second writeback circuitry coupled to the second memory cell array and the data sense amplifier latch circuitry.
 13. The apparatus according to claim 1, wherein the first bit line input circuitry is configured to couple the first memory cell array to the data sense amplifier latch circuitry via a bit line and the second bit line input circuitry is configured to couple the second memory cell array to the data sense amplifier latch circuitry via the bit line.
 14. A method for reading from and writing to a semiconductor memory device comprising: arranging a first plurality of memory cells in a matrix of rows and columns in a first memory cell array; arranging a second plurality of memory cells in a matrix of row and columns in a second memory cell array; coupling the first memory cell array to a first input node of a data sense amplifier latch circuitry via a first bit line input circuitry; coupling the second memory cell array to a second input node of the data sense amplifier latch circuitry via a second bit line input circuitry; coupling a precharge circuitry to the first input node and the second input node for precharging the first input node and the second input node to a first pre-charged voltage level and a second pre-charged voltage level, respectively; and coupling a keeper circuitry to the first bit line input circuitry and the second bit line input circuitry for maintaining the first pre-charged voltage level at the first input node and the second pre-charged voltage level at the second input node, respectively.
 15. The method according to claim 14, further comprising coupling an input/output circuitry to the data sense amplifier latch circuitry to output one or more data states of at least one of the first memory cell array and the second memory cell array detected by the data sense amplifier latch circuitry.
 16. The method according to claim 14, further comprising coupling a first writeback circuitry to the first memory cell array and the data sense amplifier latch circuitry to perform a write operation.
 17. The method according to claim 16, further comprising coupling a second writeback circuitry to the second memory cell array and the data sense amplifier latch circuitry to perform a write operation.
 18. The method according to claim 14, wherein coupling the first memory cell array to the first input node of the data sense amplifier latch circuitry is via a bit line and coupling the second memory cell array to the second input node of the data sense amplifier latch circuitry is via the bit line.
 19. An apparatus comprising: a first memory cell array comprising a first plurality of memory cells arranged in a matrix of rows and columns; a second memory cell array comprising a second plurality of memory cells arranged in a matrix of row and columns; a data sense amplifier latch circuitry comprising a first input node and a second input node; a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry; a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry; a precharge circuitry coupled to the first input node and the second input node for precharging the first input node and the second input node to a first pre-charged voltage level and a second pre-charged voltage level, respectively; and a writeback circuitry coupled to the first bit line input circuitry and the second bit line input circuitry for writing a data state stored in the data sense amplifier latch circuitry back to at least one first memory cell in the first plurality of memory cells and at least one second memory cell in the second plurality of memory cells, respectively.
 20. A method for reading from and writing to a semiconductor memory device comprising: arranging a first plurality of memory cells in a matrix of rows and columns in a first memory cell array; arranging a second plurality of memory cells in a matrix of row and columns in a second memory cell array; coupling the first memory cell array to a first input node of a data sense amplifier latch circuitry via a first bit line input circuitry; coupling the second memory cell array to a second input node of the data sense amplifier latch circuitry via a second bit line input circuitry; coupling a precharge circuitry to the first input node and the second input node for precharging the first input node and the second input node to a first pre-charged voltage level and a second pre-charged voltage level, respectively; and coupling a writeback circuitry to the first bit line input circuitry and the second bit line input circuitry for writing a data state stored in the data sense amplifier latch circuitry back to at least one first memory cell in the first plurality of memory cells and at least one second memory cell in the second plurality of memory cells, respectively.
 21. The apparatus according to claim 5, wherein the hold circuitry in the first bit line input circuitry comprises a transistor to provide a predetermined retention time for a data state stored in the first memory cell array.
 22. The apparatus according to claim 6, wherein the hold circuitry in the second bit line input circuitry comprises a transistor to provide a predetermined retention time for a data state stored in the second memory cell array. 